Commit 3be1406a authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Add timing generator count to resource pool. 



Use tg count in resource pool for further reference.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 05133ac8

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -849,6 +849,7 @@ static bool construct( 
	*************************************************/

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = res_cap.num_timing_generator;

	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1152,7 +1152,7 @@ static bool construct( 


	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

	pool->base.underlay_pipe_index = pool->base.pipe_count;



	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 150;

	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1100,6 +1100,7 @@ static bool construct( 
	 *************************************************/

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -831,6 +831,7 @@ static bool construct( 


	/* TODO: Fill more data from GreenlandAsicCapability.cpp */

	pool->base.pipe_count = res_cap.num_timing_generator;

	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;



	dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

+3 −0
Original line number Diff line number Diff line
@@ -790,6 +790,7 @@ static bool dce80_construct( 
	 *************************************************/

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = res_cap.num_timing_generator;

	pool->base.timing_generator_count = res_cap.num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;
@@ -955,6 +956,7 @@ static bool dce81_construct( 
	 *************************************************/

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = res_cap_81.num_timing_generator;

	pool->base.timing_generator_count = res_cap_81.num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;
@@ -1120,6 +1122,7 @@ static bool dce83_construct( 
	 *************************************************/

	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = res_cap_83.num_timing_generator;

	pool->base.timing_generator_count = res_cap_83.num_timing_generator;

	dc->caps.max_downscale_ratio = 200;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;

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