Commit 3ba731da authored Mar 14, 2017 by James Hogan

KVM: MIPS/VZ: Emulate hit CACHE ops for Octeon III



Octeon III doesn't implement the optional GuestCtl0.CG bit to allow
guest mode to execute virtual address based CACHE instructions, so
implement emulation of a few important ones specifically for Octeon III
in response to a GPSI exception.

Currently the main reason to perform these operations is for icache
synchronisation, so they are implemented as a simple icache flush with
local_flush_icache_range().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

parent 824533ad

arch/mips/kvm/vz.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -1105,6 +1105,17 @@ static enum emulation_result kvm_vz_gpsi_cache(union mips_instruction inst,
		case Index_Writeback_Inv_D:
		flush_dcache_line_indexed(va);
		return EMULATE_DONE;
		case Hit_Invalidate_I:
		case Hit_Invalidate_D:
		case Hit_Writeback_Inv_D:
		if (boot_cpu_type() == CPU_CAVIUM_OCTEON3) {
		/* We can just flush entire icache */
		local_flush_icache_range(0, 0);
		return EMULATE_DONE;
		}

		/* So far, other platforms support guest hit cache ops */
		break;
		default:
		break;
		};

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