Commit 3b2c1bfe authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: remove the i915_dpio debugfs entry 



There are igt tools that can read/write the DPIO registers, so having a
debugfs entry for only some of those registers is somewhat arbitrary /
redundant. Remove it.

v2:
- instead of fixing the entry by taking a power domain reference around
  the register accesses, remove the entry (Ville)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 91ca689a

drivers/gpu/drm/i915/i915_debugfs.c

+0 −48
Original line number Diff line number Diff line
@@ -1903,53 +1903,6 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 
	return 0;

}



static int i915_dpio_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;





	if (!IS_VALLEYVIEW(dev)) {

		seq_puts(m, "unsupported\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev_priv->dpio_lock);

	if (ret)

		return ret;



	seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));



	seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));

	seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));



	seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));

	seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));



	seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));

	seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));



	seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));

	seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));



	seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));



	mutex_unlock(&dev_priv->dpio_lock);



	return 0;

}



static int i915_llc(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3808,7 +3761,6 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},

	{"i915_swizzle_info", i915_swizzle_info, 0},

	{"i915_ppgtt_info", i915_ppgtt_info, 0},

	{"i915_dpio", i915_dpio_info, 0},

	{"i915_llc", i915_llc, 0},

	{"i915_edp_psr_status", i915_edp_psr_status, 0},

	{"i915_sink_crc_eDP1", i915_sink_crc, 0},

CRA Git | Maintained and supported by SUSTech CRA and CCSE