Commit 3af9571c authored Jul 20, 2020 by Zenghui Yu Committed by Marc Zyngier Jul 27, 2020

irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
register-based invalidation operation for a vPEID not mapped to that RD,
or another RD within the same CommonLPIAff group.

To follow this rule, commit f3a05921 ("irqchip/gic-v4.1: Ensure mutual
exclusion between vPE affinity change and RD access") tried to address the
race between the RD accesses and the vPE affinity change, but somehow
forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
evaluating vpe->col_idx to fix it.

Fixes: f3a05921 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200720092328.708-1-yuzenghui@huawei.com

parent 9808357f

drivers/irqchip/irq-gic-v3-its.c

+7 −3

Original line number	Diff line number	Diff line
		@@ -4079,18 +4079,22 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
		static void its_vpe_4_1_invall(struct its_vpe *vpe)
		{
		void __iomem *rdbase;
		unsigned long flags;
		u64 val;
		int cpu;

		val = GICR_INVALLR_V;
		val \|= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);

		/* Target the redistributor this vPE is currently known on */
		raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
		cpu = vpe_to_cpuid_lock(vpe, &flags);
		raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
		rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
		gic_write_lpir(val, rdbase + GICR_INVALLR);

		wait_for_syncr(rdbase);
		raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
		raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
		vpe_to_cpuid_unlock(vpe, flags);
		}

		static int its_vpe_4_1_set_vcpu_affinity(struct irq_data d, void vcpu_info)

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