Commit 3ae9af7c authored by Nishanth Menon's avatar Nishanth Menon
Browse files

bus: omap_l3_noc: convert target information into a structure 



Currently the target instance information is organized indexed by bit
field offset into multiple arrays.

1. We currently have offsets specific to each target associated with each
clock domains are in seperate arrays:

l3_targ_inst_clk1
l3_targ_inst_clk2
l3_targ_inst_clk3

2. Then they are organized per master index in l3_targ.

3. We have names in l3_targ_inst_name as an array to array of strings
corresponding to the above with offsets.

Simplify the same by defining a structure for information containing
both target offset and name. this is then stored in arrays per domain
and organized into an array indexed off domain.

The array is still indexed based on bit field offset.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: default avatarDarren Etheridge <detheridge@ti.com>
Tested-by: default avatarSekhar Nori <nsekhar@ti.com>
parent f0a6e654

drivers/bus/omap_l3_noc.c

+4 −5
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 
	void __iomem *base, *l3_targ_base;

	void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;

	char *target_name, *master_name = "UN IDENTIFIED";

	struct l3_target_data *l3_targ_inst;



	/* Get the Type of interrupt */

	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -74,9 +75,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 
		if (err_reg) {

			/* Identify the source from control status register */

			err_src = __ffs(err_reg);

			l3_targ_inst = &l3_targ[i][err_src];

			target_name = l3_targ_inst->name;

			l3_targ_base = base + l3_targ_inst->offset;



			/* Read the stderrlog_main_source from clk domain */

			l3_targ_base = base + l3_targ[i][err_src];

			l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;

			l3_targ_slvofslsb = l3_targ_base +

					    L3_TARG_STDERRLOG_SLVOFSLSB;
@@ -88,8 +91,6 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 


			switch (std_err_main & CUSTOM_ERROR) {

			case STANDARD_ERROR:

				target_name =

					l3_targ_inst_name[i][err_src];

				WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",

					target_name,

					readl_relaxed(l3_targ_slvofslsb));
@@ -99,8 +100,6 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 
				break;



			case CUSTOM_ERROR:

				target_name =

					l3_targ_inst_name[i][err_src];

				for (k = 0; k < NUM_OF_L3_MASTERS; k++) {

					if (masterid == l3_masters[k].id)

						master_name =

drivers/bus/omap_l3_noc.h

+50 −79
Original line number Diff line number Diff line
@@ -43,51 +43,62 @@ struct l3_masters_data { 
	char *name;

};



/**

 * struct l3_target_data - L3 Target information

 * @offset:	Offset from base for L3 Target

 * @name:	Target name

 *

 * Target information is organized indexed by bit field definitions.

 */

struct l3_target_data {

	u32 offset;

	char *name;

};



static u32 l3_flagmux[L3_MODULES] = {

	0x500,

	0x1000,

	0X0200

};



/* L3 Target standard Error register offsets */

static u32 l3_targ_inst_clk1[] = {

	0x100, /* DMM1 */

	0x200, /* DMM2 */

	0x300, /* ABE */

	0x400, /* L4CFG */

	0x600,  /* CLK2 PWR DISC */

	0x0,	/* Host CLK1 */

	0x900	/* L4 Wakeup */

static struct l3_target_data l3_target_inst_data_clk1[] = {

	{0x100,	"DMM1",},

	{0x200,	"DMM2",},

	{0x300,	"ABE",},

	{0x400,	"L4CFG",},

	{0x600,	"CLK2PWRDISC",},

	{0x0,	"HOSTCLK1",},

	{0x900,	"L4WAKEUP",},

};



static u32 l3_targ_inst_clk2[] = {

	0x500, /* CORTEX M3 */

	0x300, /* DSS */

	0x100, /* GPMC */

	0x400, /* ISS */

	0x700, /* IVAHD */

	0xD00, /* missing in TRM  corresponds to AES1*/

	0x900, /* L4 PER0*/

	0x200, /* OCMRAM */

	0x100, /* missing in TRM corresponds to GPMC sERROR*/

	0x600, /* SGX */

	0x800, /* SL2 */

	0x1600, /* C2C */

	0x1100,	/* missing in TRM corresponds PWR DISC CLK1*/

	0xF00, /* missing in TRM corrsponds to SHA1*/

	0xE00, /* missing in TRM corresponds to AES2*/

	0xC00, /* L4 PER3 */

	0xA00, /* L4 PER1*/

	0xB00, /* L4 PER2*/

	0x0, /* HOST CLK2 */

	0x1800, /* CAL */

	0x1700 /* LLI */

static struct l3_target_data l3_target_inst_data_clk2[] = {

	{0x500,	"CORTEXM3",},

	{0x300,	"DSS",},

	{0x100,	"GPMC",},

	{0x400,	"ISS",},

	{0x700,	"IVAHD",},

	{0xD00,	"AES1",},

	{0x900,	"L4PER0",},

	{0x200,	"OCMRAM",},

	{0x100,	"GPMCsERROR",},

	{0x600,	"SGX",},

	{0x800,	"SL2",},

	{0x1600, "C2C",},

	{0x1100, "PWRDISCCLK1",},

	{0xF00,	"SHA1",},

	{0xE00,	"AES2",},

	{0xC00,	"L4PER3",},

	{0xA00,	"L4PER1",},

	{0xB00,	"L4PER2",},

	{0x0,	"HOSTCLK2",},

	{0x1800, "CAL",},

	{0x1700, "LLI",},

};



static u32 l3_targ_inst_clk3[] = {

	0x0100	/* EMUSS */,

	0x0300, /* DEBUGSS_CT_TBR */

	0x0 /* HOST CLK3 */

static struct l3_target_data l3_target_inst_data_clk3[] = {

	{0x0100, "EMUSS",},

	{0x0300, "DEBUG SOURCE",},

	{0x0,	"HOST CLK3",},

};



static struct l3_masters_data l3_masters[] = {
@@ -118,50 +129,10 @@ static struct l3_masters_data l3_masters[] = { 
	{ 0xC8, "USBHOSTFS"}

};



static char *l3_targ_inst_name[L3_MODULES][21] = {

	{

		"DMM1",

		"DMM2",

		"ABE",

		"L4CFG",

		"CLK2 PWR DISC",

		"HOST CLK1",

		"L4 WAKEUP"

	},

	{

		"CORTEX M3" ,

		"DSS ",

		"GPMC ",

		"ISS ",

		"IVAHD ",

		"AES1",

		"L4 PER0",

		"OCMRAM ",

		"GPMC sERROR",

		"SGX ",

		"SL2 ",

		"C2C ",

		"PWR DISC CLK1",

		"SHA1",

		"AES2",

		"L4 PER3",

		"L4 PER1",

		"L4 PER2",

		"HOST CLK2",

		"CAL",

		"LLI"

	},

	{

		"EMUSS",

		"DEBUG SOURCE",

		"HOST CLK3"

	},

};



static u32 *l3_targ[L3_MODULES] = {

	l3_targ_inst_clk1,

	l3_targ_inst_clk2,

	l3_targ_inst_clk3,

static struct l3_target_data *l3_targ[L3_MODULES] = {

	l3_target_inst_data_clk1,

	l3_target_inst_data_clk2,

	l3_target_inst_data_clk3,

};



struct omap_l3 {

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