Commit 3abda7ca authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux into arm/drivers 

Reset controller updates for v5.6

This tag adds support for the Nuvoton NPCM, Intel Gatway SoC, and
Broadcom BCM7216 RESCAL reset controllers, adds missing SCSSI reset
controls for newer Uniphier SoCs, aligns the program flow in the
devm_reset_controller_register, __devm_reset_control_get, and
devm_reset_control_array_get functions for better consistency,
and allows to build the Qcom AOSS reset driver as a module.

This is based on v5.5-rc3 because the core patch depends on commit
db238086 ("reset: Do not register resource data for missing
resets").

* tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux:
  reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate
  reset: Add Broadcom STB RESCAL reset controller
  dt-bindings: reset: Document BCM7216 RESCAL reset controller
  reset: intel: Add system reset controller driver
  dt-bindings: reset: Add YAML schemas for the Intel Reset controller
  reset: uniphier: Add SCSSI reset control for each channel
  reset: Align logic and flow in managed helpers
  reset: npcm: add NPCM reset controller driver
  dt-bindings: reset: Add binding constants for NPCM7xx reset controller
  dt-bindings: reset: add NPCM reset controller documentation

Link: https://lore.kernel.org/r/dbbb2ca7490a0146d9ba632fd4d9f38063e03e9f.camel@pengutronix.de


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ef832e4c e2d5e833

Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml

0 → 100644
+37 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2020 Broadcom

%YAML 1.2

---

$id: "http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: BCM7216 RESCAL reset controller



description: This document describes the BCM7216 RESCAL reset controller which is responsible for controlling the reset of the SATA and PCIe0/1 instances on BCM7216.



maintainers:

  - Florian Fainelli <f.fainelli@gmail.com>

  - Jim Quinlan <jim2101024@gmail.com>



properties:

  compatible:

    const: brcm,bcm7216-pcie-sata-rescal



  reg:

    maxItems: 1



  "#reset-cells":

    const: 0



required:

  - compatible

  - reg

  - "#reset-cells"



examples:

  - |

    reset-controller@8b2c800 {

          compatible = "brcm,bcm7216-pcie-sata-rescal";

          reg = <0x8b2c800 0x10>;

          #reset-cells = <0>;

    };

Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml

0 → 100644
+63 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: System Reset Controller on Intel Gateway SoCs



maintainers:

  - Dilip Kota <eswara.kota@linux.intel.com>



properties:

  compatible:

    enum:

      - intel,rcu-lgm

      - intel,rcu-xrx200



  reg:

    description: Reset controller registers.

    maxItems: 1



  intel,global-reset:

    description: Global reset register offset and bit offset.

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32-array

      - maxItems: 2



  "#reset-cells":

    minimum: 2

    maximum: 3

    description: |

      First cell is reset request register offset.

      Second cell is bit offset in reset request register.

      Third cell is bit offset in reset status register.

      For LGM SoC, reset cell count is 2 as bit offset in

      reset request and reset status registers is same. Whereas

      3 for legacy SoCs as bit offset differs.



required:

  - compatible

  - reg

  - intel,global-reset

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    rcu0: reset-controller@e0000000 {

        compatible = "intel,rcu-lgm";

        reg = <0xe0000000 0x20000>;

        intel,global-reset = <0x10 30>;

        #reset-cells = <2>;

    };



    pwm: pwm@e0d00000 {

        status = "disabled";

        compatible = "intel,lgm-pwm";

        reg = <0xe0d00000 0x30>;

        clocks = <&cgu0 1>;

        #pwm-cells = <2>;

        resets = <&rcu0 0x30 21>;

    };

Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt

0 → 100644
+32 −0
Original line number Diff line number Diff line 
Nuvoton NPCM Reset controller



Required properties:

- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC

- reg : specifies physical base address and size of the register.

- #reset-cells: must be set to 2



Optional property:

- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.

  NPCM7xx contain four software reset that represent numbers 1 to 4.



  If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.



Example:

	rstc: rstc@f0801000 {

		compatible = "nuvoton,npcm750-reset";

		reg = <0xf0801000 0x70>;

		#reset-cells = <2>;

		nuvoton,sw-reset-number = <2>;

	};



Specifying reset lines connected to IP NPCM7XX modules

======================================================

example:



        spi0: spi@..... {

                ...

                resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;

                ...

        };



The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.

drivers/reset/Kconfig

+24 −1
Original line number Diff line number Diff line
@@ -49,6 +49,13 @@ config RESET_BRCMSTB 
	  This enables the reset controller driver for Broadcom STB SoCs using

	  a SUN_TOP_CTRL_SW_INIT style controller.



config RESET_BRCMSTB_RESCAL

	bool "Broadcom STB RESCAL reset controller"

	default ARCH_BRCMSTB || COMPILE_TEST

	help

	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on

	  BCM7216.



config RESET_HSDK

	bool "Synopsys HSDK Reset Driver"

	depends on HAS_IOMEM
@@ -64,6 +71,15 @@ config RESET_IMX7 
	help

	  This enables the reset controller driver for i.MX7 SoCs.



config RESET_INTEL_GW

	bool "Intel Reset Controller Driver"

	depends on OF

	select REGMAP_MMIO

	help

	  This enables the reset controller driver for Intel Gateway SoCs.

	  Say Y to control the reset signals provided by reset controller.

	  Otherwise, say N.



config RESET_LANTIQ

	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST

	default SOC_TYPE_XWAY
@@ -89,6 +105,13 @@ config RESET_MESON_AUDIO_ARB 
	  This enables the reset driver for Audio Memory Arbiter of

	  Amlogic's A113 based SoCs



config RESET_NPCM

	bool "NPCM BMC Reset Driver" if COMPILE_TEST

	default ARCH_NPCM

	help

	  This enables the reset controller driver for Nuvoton NPCM

	  BMC SoCs.



config RESET_OXNAS

	bool
@@ -99,7 +122,7 @@ config RESET_PISTACHIO 
	  This enables the reset driver for ImgTec Pistachio SoCs.



config RESET_QCOM_AOSS

	bool "Qcom AOSS Reset Driver"

	tristate "Qcom AOSS Reset Driver"

	depends on ARCH_QCOM || COMPILE_TEST

	help

	  This enables the AOSS (always on subsystem) reset driver

drivers/reset/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -8,12 +8,15 @@ obj-$(CONFIG_RESET_ATH79) += reset-ath79.o 
obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o

obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o

obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o

obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o

obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o

obj-$(CONFIG_RESET_IMX7) += reset-imx7.o

obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o

obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o

obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o

obj-$(CONFIG_RESET_MESON) += reset-meson.o

obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o

obj-$(CONFIG_RESET_NPCM) += reset-npcm.o

obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o

obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o

obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o

CRA Git | Maintained and supported by SUSTech CRA and CCSE