Commit 3aa883ac authored by Jiange Zhao's avatar Jiange Zhao Committed by Alex Deucher
Browse files

drm/amdgpu/SRIOV: Extend VF reset request wait period 



In Virtualization case, when one VF is sending too many
FLR requests, hypervisor would stop responding to this
VF's request for a long period of time. This is called
event guard. During this period of cooling time, guest
driver should wait instead of doing other things. After
this period of time, guest driver would resume reset
process and return to normal.

Currently, guest driver would wait 12 seconds and return fail
if it doesn't get response from host.

Solution: extend this waiting time in guest driver and poll
response periodically. Poll happens every 6 seconds and it will
last for 60 seconds.

v2: change the max repetition times from number to macro.

Signed-off-by: default avatarJiange Zhao <Jiange.Zhao@amd.com>
Acked-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 325f4b59

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

+10 −1
Original line number Diff line number Diff line
@@ -187,7 +187,16 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, 


static int xgpu_ai_request_reset(struct amdgpu_device *adev)

{

	return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);

	int ret, i = 0;



	while (i < AI_MAILBOX_POLL_MSG_REP_MAX) {

		ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);

		if (!ret)

			break;

		i++;

	}



	return ret;

}



static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h

+2 −1
Original line number Diff line number Diff line
@@ -25,8 +25,9 @@ 
#define __MXGPU_AI_H__



#define AI_MAILBOX_POLL_ACK_TIMEDOUT	500

#define AI_MAILBOX_POLL_MSG_TIMEDOUT	12000

#define AI_MAILBOX_POLL_MSG_TIMEDOUT	6000

#define AI_MAILBOX_POLL_FLR_TIMEDOUT	5000

#define AI_MAILBOX_POLL_MSG_REP_MAX	11



enum idh_request {

	IDH_REQ_GPU_INIT_ACCESS = 1,

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

+10 −1
Original line number Diff line number Diff line
@@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, 


static int xgpu_nv_request_reset(struct amdgpu_device *adev)

{

	return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);

	int ret, i = 0;



	while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {

		ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);

		if (!ret)

			break;

		i++;

	}



	return ret;

}



static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define NV_MAILBOX_POLL_ACK_TIMEDOUT	500

#define NV_MAILBOX_POLL_MSG_TIMEDOUT	6000

#define NV_MAILBOX_POLL_FLR_TIMEDOUT	5000

#define NV_MAILBOX_POLL_MSG_REP_MAX	11



enum idh_request {

	IDH_REQ_GPU_INIT_ACCESS = 1,

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