Commit 3a979e8c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - Remove HAS_DMA config dependencies

 - New STMicroelectronics STM32 IPCC driver

 - Enable QCom driver to run more controllers

 - Fixed return code from null to ptr-err for Brcm driver

 - Fix kconfig dependencies for the HiSilicon driver

* tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX
  mailbox: Add support for Qualcomm SDM845 SoCs
  dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs
  mailbox: bcm2835: Fix of_xlate return value
  mailbox: qcom: Add msm8998 hmss compatible
  mailbox: add STMicroelectronics STM32 IPCC driver
  dt-bindings: mailbox: add STMicroelectronics STM32 IPCC binding
  mailbox: Remove depends on HAS_DMA in case of platform dependency
parents a1cdde8c f83d1cfc

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt

+2 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ platforms. 
	Definition: must be one of:

		    "qcom,msm8916-apcs-kpss-global",

		    "qcom,msm8996-apcs-hmss-global"

		    "qcom,msm8998-apcs-hmss-global"

		    "qcom,sdm845-apss-shared"



- reg:

	Usage: required

Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt

0 → 100644
+47 −0
Original line number Diff line number Diff line 
* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)



The IPCC block provides a non blocking signaling mechanism to post and

retrieve messages in an atomic way between two processors.

It provides the signaling for N bidirectionnal channels. The number of channels

(N) can be read from a dedicated register.



Required properties:

- compatible:   Must be "st,stm32mp1-ipcc"

- reg:          Register address range (base address and length)

- st,proc-id:   Processor id using the mailbox (0 or 1)

- clocks:       Input clock

- interrupt-names: List of names for the interrupts described by the interrupt

                   property. Must contain the following entries:

                   - "rx"

                   - "tx"

                   - "wakeup"

- interrupts:   Interrupt specifiers for "rx channel occupied", "tx channel

                free" and "system wakeup".

- #mbox-cells:  Number of cells required for the mailbox specifier. Must be 1.

                The data contained in the mbox specifier of the "mboxes"

                property in the client node is the mailbox channel index.



Optional properties:

- wakeup-source: Flag to indicate whether this device can wake up the system







Example:

	ipcc: mailbox@4c001000 {

		compatible = "st,stm32mp1-ipcc";

		#mbox-cells = <1>;

		reg = <0x4c001000 0x400>;

		st,proc-id = <0>;

		interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,

				      <&intc GIC_SPI 101 IRQ_TYPE_NONE>,

				      <&aiec 62 1>;

		interrupt-names = "rx", "tx", "wakeup";

		clocks = <&rcc_clk IPCC>;

		wakeup-source;

	}



Client:

	mbox_test {

		...

		mboxes = <&ipcc 0>, <&ipcc 1>;

	};

drivers/mailbox/Kconfig

+16 −6
Original line number Diff line number Diff line
@@ -109,16 +109,20 @@ config TI_MESSAGE_MANAGER 
	  platform has support for the hardware block.



config HI3660_MBOX

	tristate "Hi3660 Mailbox"

	depends on ARCH_HISI && OF

	tristate "Hi3660 Mailbox" if EXPERT

	depends on (ARCH_HISI || COMPILE_TEST)

	depends on OF

	default ARCH_HISI

	help

	  An implementation of the hi3660 mailbox. It is used to send message

	  between application processors and other processors/MCU/DSP. Select

	  Y here if you want to use Hi3660 mailbox controller.



config HI6220_MBOX

	tristate "Hi6220 Mailbox"

	depends on ARCH_HISI

	tristate "Hi6220 Mailbox" if EXPERT

	depends on (ARCH_HISI || COMPILE_TEST)

	depends on OF

	default ARCH_HISI

	help

	  An implementation of the hi6220 mailbox. It is used to send message

	  between application processors and MCU. Say Y here if you want to
@@ -162,7 +166,6 @@ config XGENE_SLIMPRO_MBOX 
config BCM_PDC_MBOX

	tristate "Broadcom FlexSparx DMA Mailbox"

	depends on ARCH_BCM_IPROC || COMPILE_TEST

	depends on HAS_DMA

	help

	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,

	  which provides access to various offload engines on Broadcom
@@ -172,11 +175,18 @@ config BCM_FLEXRM_MBOX 
	tristate "Broadcom FlexRM Mailbox"

	depends on ARM64

	depends on ARCH_BCM_IPROC || COMPILE_TEST

	depends on HAS_DMA

	select GENERIC_MSI_IRQ_DOMAIN

	default m if ARCH_BCM_IPROC

	help

	  Mailbox implementation of the Broadcom FlexRM ring manager,

	  which provides access to various offload engines on Broadcom

	  SoCs. Say Y here if you want to use the Broadcom FlexRM.



config STM32_IPCC

	tristate "STM32 IPCC Mailbox"

	depends on MACH_STM32MP157

	help

	  Mailbox implementation for STMicroelectonics STM32 family chips

	  with hardware for Inter-Processor Communication Controller (IPCC)

	  between processors. Say Y here if you want to have this support.

endif

drivers/mailbox/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -38,3 +38,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o 
obj-$(CONFIG_QCOM_APCS_IPC)	+= qcom-apcs-ipc-mailbox.o



obj-$(CONFIG_TEGRA_HSP_MBOX)	+= tegra-hsp.o



obj-$(CONFIG_STM32_IPCC) 	+= stm32-ipcc.o

drivers/mailbox/bcm2835-mailbox.c

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox, 
		    const struct of_phandle_args *sp)

{

	if (sp->args_count != 0)

		return NULL;

		return ERR_PTR(-EINVAL);



	return &mbox->chans[0];

}

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