Commit 3a858ba3 authored by Anirudh Venkataramanan's avatar Anirudh Venkataramanan Committed by Jeff Kirsher
Browse files

ice: Add support for VSI allocation and deallocation 



This patch introduces data structures and functions to alloc/free
VSIs. The driver represents a VSI using the ice_vsi structure.

Some noteworthy points about VSI allocation:

1) A VSI is allocated in the firmware using the "add VSI" admin queue
   command (implemented as ice_aq_add_vsi). The firmware returns an
   identifier for the allocated VSI. The VSI context is used to program
   certain aspects (loopback, queue map, etc.) of the VSI's configuration.

2) A VSI is deleted using the "free VSI" admin queue command (implemented
   as ice_aq_free_vsi).

3) The driver represents a VSI using struct ice_vsi. This is allocated
   and initialized as part of the ice_vsi_alloc flow, and deallocated
   as part of the ice_vsi_delete flow.

4) Once the VSI is created, a netdev is allocated and associated with it.
   The VSI's ring and vector related data structures are also allocated
   and initialized.

5) A VSI's queues can either be contiguous or scattered. To do this, the
   driver maintains a bitmap (vsi->avail_txqs) which is kept in sync with
   the firmware's VSI queue allocation imap. If the VSI can't get a
   contiguous queue allocation, it will fallback to scatter. This is
   implemented in ice_vsi_get_qs which is called as part of the VSI setup
   flow. In the release flow, the VSI's queues are released and the bitmap
   is updated to reflect this by ice_vsi_put_qs.

CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: default avatarShannon Nelson <shannon.nelson@oracle.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 940b61af

drivers/net/ethernet/intel/ice/ice.h

+72 −0
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ 
#include <linux/netdevice.h>

#include <linux/compiler.h>

#include <linux/etherdevice.h>

#include <linux/cpumask.h>

#include <linux/if_vlan.h>

#include <linux/pci.h>

#include <linux/workqueue.h>

#include <linux/aer.h>
@@ -18,6 +20,7 @@ 
#include <linux/timer.h>

#include <linux/delay.h>

#include <linux/bitmap.h>

#include <linux/log2.h>

#include <linux/if_bridge.h>

#include "ice_devids.h"

#include "ice_type.h"
@@ -27,17 +30,43 @@ 
#include "ice_sched.h"



#define ICE_BAR0		0

#define ICE_DFLT_NUM_DESC	128

#define ICE_REQ_DESC_MULTIPLE	32

#define ICE_INT_NAME_STR_LEN	(IFNAMSIZ + 16)

#define ICE_AQ_LEN		64

#define ICE_MIN_MSIX		2

#define ICE_NO_VSI		0xffff

#define ICE_MAX_VSI_ALLOC	130

#define ICE_MAX_TXQS		2048

#define ICE_MAX_RXQS		2048

#define ICE_VSI_MAP_CONTIG	0

#define ICE_VSI_MAP_SCATTER	1

#define ICE_MAX_SCATTER_TXQS	16

#define ICE_MAX_SCATTER_RXQS	16

#define ICE_RES_VALID_BIT	0x8000

#define ICE_RES_MISC_VEC_ID	(ICE_RES_VALID_BIT - 1)

#define ICE_INVAL_Q_INDEX	0xffff



#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)



#define ICE_MAX_MTU	(ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \

			 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)



#define ICE_UP_TABLE_TRANSLATE(val, i) \

		(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \

		  ICE_AQ_VSI_UP_TABLE_UP##i##_M)



struct ice_tc_info {

	u16 qoffset;

	u16 qcount;

};



struct ice_tc_cfg {

	u8 numtc; /* Total number of enabled TCs */

	u8 ena_tc; /* TX map */

	struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];

};



struct ice_res_tracker {

	u16 num_entries;

	u16 search_hint;
@@ -61,8 +90,47 @@ enum ice_state { 
/* struct that defines a VSI, associated with a dev */

struct ice_vsi {

	struct net_device *netdev;

	struct ice_sw *vsw;		 /* switch this VSI is on */

	struct ice_pf *back;		 /* back pointer to PF */

	struct ice_port_info *port_info; /* back pointer to port_info */

	struct ice_ring **rx_rings;	 /* rx ring array */

	struct ice_ring **tx_rings;	 /* tx ring array */

	struct ice_q_vector **q_vectors; /* q_vector array */

	DECLARE_BITMAP(state, __ICE_STATE_NBITS);

	int num_q_vectors;

	int base_vector;

	enum ice_vsi_type type;

	u16 vsi_num;			 /* HW (absolute) index of this VSI */

	u16 idx;			 /* software index in pf->vsi[] */



	/* Interrupt thresholds */

	u16 work_lmt;



	struct ice_aqc_vsi_props info;	 /* VSI properties */



	/* queue information */

	u8 tx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */

	u8 rx_mapping_mode;		 /* ICE_MAP_MODE_[CONTIG|SCATTER] */

	u16 txq_map[ICE_MAX_TXQS];	 /* index in pf->avail_txqs */

	u16 rxq_map[ICE_MAX_RXQS];	 /* index in pf->avail_rxqs */

	u16 alloc_txq;			 /* Allocated Tx queues */

	u16 num_txq;			 /* Used Tx queues */

	u16 alloc_rxq;			 /* Allocated Rx queues */

	u16 num_rxq;			 /* Used Rx queues */

	u16 num_desc;

	struct ice_tc_cfg tc_cfg;

} ____cacheline_internodealigned_in_smp;



/* struct that defines an interrupt vector */

struct ice_q_vector {

	struct ice_vsi *vsi;

	cpumask_t affinity_mask;

	struct napi_struct napi;

	struct ice_ring_container rx;

	struct ice_ring_container tx;

	u16 v_idx;			/* index in the vsi->q_vector array. */

	u8 num_ring_tx;			/* total number of tx rings in vector */

	u8 num_ring_rx;			/* total number of rx rings in vector */

} ____cacheline_internodealigned_in_smp;



enum ice_pf_flags {
@@ -103,6 +171,10 @@ struct ice_pf { 
	char int_name[ICE_INT_NAME_STR_LEN];

};



struct ice_netdev_priv {

	struct ice_vsi *vsi;

};



/**

 * ice_irq_dynamic_ena - Enable default interrupt generation settings

 * @hw: pointer to hw struct

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+199 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 */



#define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9

#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728



struct ice_aqc_generic {

	__le32 param0;
@@ -190,6 +191,199 @@ struct ice_aqc_get_sw_cfg_resp { 
	struct ice_aqc_get_sw_cfg_resp_elem elements[1];

};



/* Add VSI (indirect 0x0210)

 * Update VSI (indirect 0x0211)

 * Get VSI (indirect 0x0212)

 * Free VSI (indirect 0x0213)

 */

struct ice_aqc_add_get_update_free_vsi {

	__le16 vsi_num;

#define ICE_AQ_VSI_NUM_S	0

#define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)

#define ICE_AQ_VSI_IS_VALID	BIT(15)

	__le16 cmd_flags;

#define ICE_AQ_VSI_KEEP_ALLOC	0x1

	u8 vf_id;

	u8 reserved;

	__le16 vsi_flags;

#define ICE_AQ_VSI_TYPE_S	0

#define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)

#define ICE_AQ_VSI_TYPE_VF	0x0

#define ICE_AQ_VSI_TYPE_VMDQ2	0x1

#define ICE_AQ_VSI_TYPE_PF	0x2

#define ICE_AQ_VSI_TYPE_EMP_MNG	0x3

	__le32 addr_high;

	__le32 addr_low;

};



/* Response descriptor for:

 * Add VSI (indirect 0x0210)

 * Update VSI (indirect 0x0211)

 * Free VSI (indirect 0x0213)

 */

struct ice_aqc_add_update_free_vsi_resp {

	__le16 vsi_num;

	__le16 ext_status;

	__le16 vsi_used;

	__le16 vsi_free;

	__le32 addr_high;

	__le32 addr_low;

};



struct ice_aqc_vsi_props {

	__le16 valid_sections;

#define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)

#define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)

#define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)

#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)

#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)

#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)

#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)

#define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)

#define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)

#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)

#define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)

	/* switch section */

	u8 sw_id;

	u8 sw_flags;

#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)

#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)

#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)

	u8 sw_flags2;

#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0

#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	\

				(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)

#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)

#define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)

	u8 veb_stat_id;

#define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0

#define ICE_AQ_VSI_SW_VEB_STAT_ID_M	(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)

#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)

	/* security section */

	u8 sec_flags;

#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)

#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)

#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S	4

#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M	(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)

#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)

	u8 sec_reserved;

	/* VLAN section */

	__le16 pvid; /* VLANS include priority bits */

	u8 pvlan_reserved[2];

	u8 port_vlan_flags;

#define ICE_AQ_VSI_PVLAN_MODE_S	0

#define ICE_AQ_VSI_PVLAN_MODE_M	(0x3 << ICE_AQ_VSI_PVLAN_MODE_S)

#define ICE_AQ_VSI_PVLAN_MODE_UNTAGGED	0x1

#define ICE_AQ_VSI_PVLAN_MODE_TAGGED	0x2

#define ICE_AQ_VSI_PVLAN_MODE_ALL	0x3

#define ICE_AQ_VSI_PVLAN_INSERT_PVID	BIT(2)

#define ICE_AQ_VSI_PVLAN_EMOD_S	3

#define ICE_AQ_VSI_PVLAN_EMOD_M	(0x3 << ICE_AQ_VSI_PVLAN_EMOD_S)

#define ICE_AQ_VSI_PVLAN_EMOD_STR_BOTH	(0x0 << ICE_AQ_VSI_PVLAN_EMOD_S)

#define ICE_AQ_VSI_PVLAN_EMOD_STR_UP	(0x1 << ICE_AQ_VSI_PVLAN_EMOD_S)

#define ICE_AQ_VSI_PVLAN_EMOD_STR	(0x2 << ICE_AQ_VSI_PVLAN_EMOD_S)

#define ICE_AQ_VSI_PVLAN_EMOD_NOTHING	(0x3 << ICE_AQ_VSI_PVLAN_EMOD_S)

	u8 pvlan_reserved2[3];

	/* ingress egress up sections */

	__le32 ingress_table; /* bitmap, 3 bits per up */

#define ICE_AQ_VSI_UP_TABLE_UP0_S	0

#define ICE_AQ_VSI_UP_TABLE_UP0_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)

#define ICE_AQ_VSI_UP_TABLE_UP1_S	3

#define ICE_AQ_VSI_UP_TABLE_UP1_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)

#define ICE_AQ_VSI_UP_TABLE_UP2_S	6

#define ICE_AQ_VSI_UP_TABLE_UP2_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)

#define ICE_AQ_VSI_UP_TABLE_UP3_S	9

#define ICE_AQ_VSI_UP_TABLE_UP3_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)

#define ICE_AQ_VSI_UP_TABLE_UP4_S	12

#define ICE_AQ_VSI_UP_TABLE_UP4_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)

#define ICE_AQ_VSI_UP_TABLE_UP5_S	15

#define ICE_AQ_VSI_UP_TABLE_UP5_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)

#define ICE_AQ_VSI_UP_TABLE_UP6_S	18

#define ICE_AQ_VSI_UP_TABLE_UP6_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)

#define ICE_AQ_VSI_UP_TABLE_UP7_S	21

#define ICE_AQ_VSI_UP_TABLE_UP7_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)

	__le32 egress_table;   /* same defines as for ingress table */

	/* outer tags section */

	__le16 outer_tag;

	u8 outer_tag_flags;

#define ICE_AQ_VSI_OUTER_TAG_MODE_S	0

#define ICE_AQ_VSI_OUTER_TAG_MODE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)

#define ICE_AQ_VSI_OUTER_TAG_NOTHING	0x0

#define ICE_AQ_VSI_OUTER_TAG_REMOVE	0x1

#define ICE_AQ_VSI_OUTER_TAG_COPY	0x2

#define ICE_AQ_VSI_OUTER_TAG_TYPE_S	2

#define ICE_AQ_VSI_OUTER_TAG_TYPE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)

#define ICE_AQ_VSI_OUTER_TAG_NONE	0x0

#define ICE_AQ_VSI_OUTER_TAG_STAG	0x1

#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100	0x2

#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100	0x3

#define ICE_AQ_VSI_OUTER_TAG_INSERT	BIT(4)

#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)

	u8 outer_tag_reserved;

	/* queue mapping section */

	__le16 mapping_flags;

#define ICE_AQ_VSI_Q_MAP_CONTIG	0x0

#define ICE_AQ_VSI_Q_MAP_NONCONTIG	BIT(0)

	__le16 q_mapping[16];

#define ICE_AQ_VSI_Q_S		0

#define ICE_AQ_VSI_Q_M		(0x7FF << ICE_AQ_VSI_Q_S)

	__le16 tc_mapping[8];

#define ICE_AQ_VSI_TC_Q_OFFSET_S	0

#define ICE_AQ_VSI_TC_Q_OFFSET_M	(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)

#define ICE_AQ_VSI_TC_Q_NUM_S		11

#define ICE_AQ_VSI_TC_Q_NUM_M		(0xF << ICE_AQ_VSI_TC_Q_NUM_S)

	/* queueing option section */

	u8 q_opt_rss;

#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S	0

#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)

#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI	0x0

#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF	0x2

#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL	0x3

#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S	2

#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M	(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)

#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S	6

#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)

#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ	(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)

#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ	(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)

#define ICE_AQ_VSI_Q_OPT_RSS_XOR	(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)

#define ICE_AQ_VSI_Q_OPT_RSS_JHASH	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)

	u8 q_opt_tc;

#define ICE_AQ_VSI_Q_OPT_TC_OVR_S	0

#define ICE_AQ_VSI_Q_OPT_TC_OVR_M	(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)

#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR	BIT(7)

	u8 q_opt_flags;

#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN	BIT(0)

	u8 q_opt_reserved[3];

	/* outer up section */

	__le32 outer_up_table; /* same structure and defines as ingress tbl */

	/* section 10 */

	__le16 sect_10_reserved;

	/* flow director section */

	__le16 fd_options;

#define ICE_AQ_VSI_FD_ENABLE		BIT(0)

#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE	BIT(1)

#define ICE_AQ_VSI_FD_PROG_ENABLE	BIT(3)

	__le16 max_fd_fltr_dedicated;

	__le16 max_fd_fltr_shared;

	__le16 fd_def_q;

#define ICE_AQ_VSI_FD_DEF_Q_S		0

#define ICE_AQ_VSI_FD_DEF_Q_M		(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)

#define ICE_AQ_VSI_FD_DEF_GRP_S	12

#define ICE_AQ_VSI_FD_DEF_GRP_M	(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)

	__le16 fd_report_opt;

#define ICE_AQ_VSI_FD_REPORT_Q_S	0

#define ICE_AQ_VSI_FD_REPORT_Q_M	(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)

#define ICE_AQ_VSI_FD_DEF_PRIORITY_S	12

#define ICE_AQ_VSI_FD_DEF_PRIORITY_M	(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)

#define ICE_AQ_VSI_FD_DEF_DROP		BIT(15)

	/* PASID section */

	__le32 pasid_id;

#define ICE_AQ_VSI_PASID_ID_S		0

#define ICE_AQ_VSI_PASID_ID_M		(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)

#define ICE_AQ_VSI_PASID_ID_VALID	BIT(31)

	u8 reserved[24];

};



/* Get Default Topology (indirect 0x0400) */

struct ice_aqc_get_topo {

	u8 port_num;
@@ -576,6 +770,7 @@ struct ice_aq_desc { 
		struct ice_aqc_query_txsched_res query_sched_res;

		struct ice_aqc_add_move_delete_elem add_move_delete_elem;

		struct ice_aqc_nvm nvm;

		struct ice_aqc_add_get_update_free_vsi vsi_cmd;

		struct ice_aqc_get_link_status get_link_status;

	} params;

};
@@ -626,6 +821,10 @@ enum ice_adminq_opc { 
	/* internal switch commands */

	ice_aqc_opc_get_sw_cfg				= 0x0200,



	/* VSI commands */

	ice_aqc_opc_add_vsi				= 0x0210,

	ice_aqc_opc_update_vsi				= 0x0211,

	ice_aqc_opc_free_vsi				= 0x0213,

	ice_aqc_opc_clear_pf_cfg			= 0x02A4,



	/* transmit scheduler commands */

drivers/net/ethernet/intel/ice/ice_main.c

+1111 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ice/ice_switch.c

+115 −0
Original line number Diff line number Diff line
@@ -50,6 +50,121 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp *buf, 
	return status;

}



/**

 * ice_aq_add_vsi

 * @hw: pointer to the hw struct

 * @vsi_ctx: pointer to a VSI context struct

 * @cd: pointer to command details structure or NULL

 *

 * Add a VSI context to the hardware (0x0210)

 */

enum ice_status

ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

	       struct ice_sq_cd *cd)

{

	struct ice_aqc_add_update_free_vsi_resp *res;

	struct ice_aqc_add_get_update_free_vsi *cmd;

	enum ice_status status;

	struct ice_aq_desc desc;



	cmd = &desc.params.vsi_cmd;

	res = (struct ice_aqc_add_update_free_vsi_resp *)&desc.params.raw;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_vsi);



	if (!vsi_ctx->alloc_from_pool)

		cmd->vsi_num = cpu_to_le16(vsi_ctx->vsi_num |

					   ICE_AQ_VSI_IS_VALID);



	cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);



	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);



	status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,

				 sizeof(vsi_ctx->info), cd);



	if (!status) {

		vsi_ctx->vsi_num = le16_to_cpu(res->vsi_num) & ICE_AQ_VSI_NUM_M;

		vsi_ctx->vsis_allocd = le16_to_cpu(res->vsi_used);

		vsi_ctx->vsis_unallocated = le16_to_cpu(res->vsi_free);

	}



	return status;

}



/**

 * ice_aq_update_vsi

 * @hw: pointer to the hw struct

 * @vsi_ctx: pointer to a VSI context struct

 * @cd: pointer to command details structure or NULL

 *

 * Update VSI context in the hardware (0x0211)

 */

enum ice_status

ice_aq_update_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

		  struct ice_sq_cd *cd)

{

	struct ice_aqc_add_update_free_vsi_resp *resp;

	struct ice_aqc_add_get_update_free_vsi *cmd;

	struct ice_aq_desc desc;

	enum ice_status status;



	cmd = &desc.params.vsi_cmd;

	resp = (struct ice_aqc_add_update_free_vsi_resp *)&desc.params.raw;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_vsi);



	cmd->vsi_num = cpu_to_le16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);



	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);



	status = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,

				 sizeof(vsi_ctx->info), cd);



	if (!status) {

		vsi_ctx->vsis_allocd = le16_to_cpu(resp->vsi_used);

		vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);

	}



	return status;

}



/**

 * ice_aq_free_vsi

 * @hw: pointer to the hw struct

 * @vsi_ctx: pointer to a VSI context struct

 * @keep_vsi_alloc: keep VSI allocation as part of this PF's resources

 * @cd: pointer to command details structure or NULL

 *

 * Get VSI context info from hardware (0x0213)

 */

enum ice_status

ice_aq_free_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

		bool keep_vsi_alloc, struct ice_sq_cd *cd)

{

	struct ice_aqc_add_update_free_vsi_resp *resp;

	struct ice_aqc_add_get_update_free_vsi *cmd;

	struct ice_aq_desc desc;

	enum ice_status status;



	cmd = &desc.params.vsi_cmd;

	resp = (struct ice_aqc_add_update_free_vsi_resp *)&desc.params.raw;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_free_vsi);



	cmd->vsi_num = cpu_to_le16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);

	if (keep_vsi_alloc)

		cmd->cmd_flags = cpu_to_le16(ICE_AQ_VSI_KEEP_ALLOC);



	status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

	if (!status) {

		vsi_ctx->vsis_allocd = le16_to_cpu(resp->vsi_used);

		vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);

	}



	return status;

}



/* ice_init_port_info - Initialize port_info with switch configuration data

 * @pi: pointer to port_info

 * @vsi_port_num: VSI number or port number

drivers/net/ethernet/intel/ice/ice_switch.h

+21 −0
Original line number Diff line number Diff line
@@ -9,6 +9,27 @@ 
#define ICE_SW_CFG_MAX_BUF_LEN 2048

#define ICE_DFLT_VSI_INVAL 0xff



/* VSI context structure for add/get/update/free operations */

struct ice_vsi_ctx {

	u16 vsi_num;

	u16 vsis_allocd;

	u16 vsis_unallocated;

	u16 flags;

	struct ice_aqc_vsi_props info;

	bool alloc_from_pool;

};



/* VSI related commands */

enum ice_status

ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

	       struct ice_sq_cd *cd);

enum ice_status

ice_aq_update_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

		  struct ice_sq_cd *cd);

enum ice_status

ice_aq_free_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,

		bool keep_vsi_alloc, struct ice_sq_cd *cd);



enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw);



#endif /* _ICE_SWITCH_H_ */

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