drm/mediatek: mtk_mt8173_hdmi_phy: Remove unnused const variables

#define RGS_HDMITX_5T1_EDG		(0xf << 4)

#define RGS_HDMITX_PLUG_TST		BIT(0)

static const u8 PREDIV[3][4] = {

	{0x0, 0x0, 0x0, 0x0},	/* 27Mhz */

	{0x1, 0x1, 0x1, 0x1},	/* 74Mhz */

	{0x1, 0x1, 0x1, 0x1}	/* 148Mhz */

};

static const u8 TXDIV[3][4] = {

	{0x3, 0x3, 0x3, 0x2},	/* 27Mhz */

	{0x2, 0x1, 0x1, 0x1},	/* 74Mhz */

	{0x1, 0x0, 0x0, 0x0}	/* 148Mhz */

};

static const u8 FBKSEL[3][4] = {

	{0x1, 0x1, 0x1, 0x1},	/* 27Mhz */

	{0x1, 0x0, 0x1, 0x1},	/* 74Mhz */

	{0x1, 0x0, 0x1, 0x1}	/* 148Mhz */

};

static const u8 FBKDIV[3][4] = {

	{19, 24, 29, 19},	/* 27Mhz */

	{19, 24, 14, 19},	/* 74Mhz */

	{19, 24, 14, 19}	/* 148Mhz */

};

static const u8 DIVEN[3][4] = {

	{0x2, 0x1, 0x1, 0x2},	/* 27Mhz */

	{0x2, 0x2, 0x2, 0x2},	/* 74Mhz */

	{0x2, 0x2, 0x2, 0x2}	/* 148Mhz */

};

static const u8 HTPLLBP[3][4] = {

	{0xc, 0xc, 0x8, 0xc},	/* 27Mhz */

	{0xc, 0xf, 0xf, 0xc},	/* 74Mhz */

	{0xc, 0xf, 0xf, 0xc}	/* 148Mhz */

};

static const u8 HTPLLBC[3][4] = {

	{0x2, 0x3, 0x3, 0x2},	/* 27Mhz */

	{0x2, 0x3, 0x3, 0x2},	/* 74Mhz */

	{0x2, 0x3, 0x3, 0x2}	/* 148Mhz */

};

static const u8 HTPLLBR[3][4] = {

	{0x1, 0x1, 0x0, 0x1},	/* 27Mhz */

	{0x1, 0x2, 0x2, 0x1},	/* 74Mhz */

	{0x1, 0x2, 0x2, 0x1}	/* 148Mhz */

};

static int mtk_hdmi_pll_prepare(struct clk_hw *hw)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);