Commit 3a74a62d authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-taprio' 



Jose Abreu says:

====================
net: stmmac: TSN support using TAPRIO API

This series adds TSN support (EST and Frame Preemption) for stmmac driver.

1) Adds the HW specific support for EST in GMAC5+ cores.

2) Adds the HW specific support for EST in XGMAC3+ cores.

3) Integrates EST HW specific support with TAPRIO scheduler API.

4) Adds the Frame Preemption suppor on stmmac TAPRIO implementation.

5) Adds the HW specific support for Frame Preemption in GMAC5+ cores.

6) Adds the HW specific support for Frame Preemption in XGMAC3+ cores.

7) Adds support for HW debug counters for Frame Preemption available in
GMAC5+ cores.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6dbb2e91 ea77b8c8

drivers/net/ethernet/stmicro/stmmac/common.h

+5 −0
Original line number Diff line number Diff line
@@ -363,6 +363,11 @@ struct dma_features { 
	unsigned int dvlan;

	unsigned int l3l4fnum;

	unsigned int arpoffsel;

	/* TSN Features */

	unsigned int estwid;

	unsigned int estdep;

	unsigned int estsel;

	unsigned int fpesel;

};



/* GMAC TX FIFO is 8K, Rx FIFO is 16K */

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

+12 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ 
#define GMAC_RXQCTRL_MCBCQEN_SHIFT	20

#define GMAC_RXQCTRL_TACPQE		BIT(21)

#define GMAC_RXQCTRL_TACPQE_SHIFT	21

#define GMAC_RXQCTRL_FPRQ		GENMASK(26, 24)

#define GMAC_RXQCTRL_FPRQ_SHIFT		24



/* MAC Packet Filtering */

#define GMAC_PACKET_FILTER_PR		BIT(0)
@@ -176,6 +178,8 @@ enum power_event { 
#define GMAC_CONFIG_SARC		GENMASK(30, 28)

#define GMAC_CONFIG_SARC_SHIFT		28

#define GMAC_CONFIG_IPC			BIT(27)

#define GMAC_CONFIG_IPG			GENMASK(26, 24)

#define GMAC_CONFIG_IPG_SHIFT		24

#define GMAC_CONFIG_2K			BIT(22)

#define GMAC_CONFIG_ACS			BIT(20)

#define GMAC_CONFIG_BE			BIT(18)
@@ -183,6 +187,7 @@ enum power_event { 
#define GMAC_CONFIG_JE			BIT(16)

#define GMAC_CONFIG_PS			BIT(15)

#define GMAC_CONFIG_FES			BIT(14)

#define GMAC_CONFIG_FES_SHIFT		14

#define GMAC_CONFIG_DM			BIT(13)

#define GMAC_CONFIG_LM			BIT(12)

#define GMAC_CONFIG_DCRS		BIT(9)
@@ -190,6 +195,9 @@ enum power_event { 
#define GMAC_CONFIG_RE			BIT(0)



/* MAC extended config */

#define GMAC_CONFIG_EIPG		GENMASK(29, 25)

#define GMAC_CONFIG_EIPG_SHIFT		25

#define GMAC_CONFIG_EIPG_EN		BIT(24)

#define GMAC_CONFIG_HDSMS		GENMASK(22, 20)

#define GMAC_CONFIG_HDSMS_SHIFT		20

#define GMAC_CONFIG_HDSMS_256		(0x2 << GMAC_CONFIG_HDSMS_SHIFT)
@@ -231,6 +239,10 @@ enum power_event { 


/* MAC HW features3 bitmap */

#define GMAC_HW_FEAT_ASP		GENMASK(29, 28)

#define GMAC_HW_FEAT_FPESEL		BIT(26)

#define GMAC_HW_FEAT_ESTWID		GENMASK(21, 20)

#define GMAC_HW_FEAT_ESTDEP		GENMASK(19, 17)

#define GMAC_HW_FEAT_ESTSEL		BIT(16)

#define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)

#define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)

#define GMAC_HW_FEAT_FRPSEL		BIT(10)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+4 −0
Original line number Diff line number Diff line
@@ -984,6 +984,8 @@ const struct stmmac_ops dwmac410_ops = { 
	.set_arp_offload = dwmac4_set_arp_offload,

	.config_l3_filter = dwmac4_config_l3_filter,

	.config_l4_filter = dwmac4_config_l4_filter,

	.est_configure = dwmac5_est_configure,

	.fpe_configure = dwmac5_fpe_configure,

};



const struct stmmac_ops dwmac510_ops = {
@@ -1027,6 +1029,8 @@ const struct stmmac_ops dwmac510_ops = { 
	.set_arp_offload = dwmac4_set_arp_offload,

	.config_l3_filter = dwmac4_config_l3_filter,

	.config_l4_filter = dwmac4_config_l4_filter,

	.est_configure = dwmac5_est_configure,

	.fpe_configure = dwmac5_fpe_configure,

};



int dwmac4_setup(struct stmmac_priv *priv)

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

+4 −0
Original line number Diff line number Diff line
@@ -404,6 +404,10 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr, 


	/* 5.10 Features */

	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;

	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;

	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;

	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;

	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;

	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;

	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;

	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;

drivers/net/ethernet/stmicro/stmmac/dwmac5.c

+118 −0
Original line number Diff line number Diff line
@@ -550,3 +550,121 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, 
	writel(val, ioaddr + MAC_PPS_CONTROL);

	return 0;

}



static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)

{

	u32 ctrl;



	writel(val, ioaddr + MTL_EST_GCL_DATA);



	ctrl = (reg << ADDR_SHIFT);

	ctrl |= gcl ? 0 : GCRR;



	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);



	ctrl |= SRWO;

	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);



	return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,

				  ctrl, !(ctrl & SRWO), 100, 5000);

}



int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,

			 unsigned int ptp_rate)

{

	u32 speed, total_offset, offset, ctrl, ctr_low;

	u32 extcfg = readl(ioaddr + GMAC_EXT_CONFIG);

	u32 mac_cfg = readl(ioaddr + GMAC_CONFIG);

	int i, ret = 0x0;

	u64 total_ctr;



	if (extcfg & GMAC_CONFIG_EIPG_EN) {

		offset = (extcfg & GMAC_CONFIG_EIPG) >> GMAC_CONFIG_EIPG_SHIFT;

		offset = 104 + (offset * 8);

	} else {

		offset = (mac_cfg & GMAC_CONFIG_IPG) >> GMAC_CONFIG_IPG_SHIFT;

		offset = 96 - (offset * 8);

	}



	speed = mac_cfg & (GMAC_CONFIG_PS | GMAC_CONFIG_FES);

	speed = speed >> GMAC_CONFIG_FES_SHIFT;



	switch (speed) {

	case 0x0:

		offset = offset * 1000; /* 1G */

		break;

	case 0x1:

		offset = offset * 400; /* 2.5G */

		break;

	case 0x2:

		offset = offset * 100000; /* 10M */

		break;

	case 0x3:

		offset = offset * 10000; /* 100M */

		break;

	default:

		return -EINVAL;

	}



	offset = offset / 1000;



	ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);

	ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);

	ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);

	ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);

	if (ret)

		return ret;



	total_offset = 0;

	for (i = 0; i < cfg->gcl_size; i++) {

		ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i] + offset, true);

		if (ret)

			return ret;



		total_offset += offset;

	}



	total_ctr = cfg->ctr[0] + cfg->ctr[1] * 1000000000;

	total_ctr += total_offset;



	ctr_low = do_div(total_ctr, 1000000000);



	ret |= dwmac5_est_write(ioaddr, CTR_LOW, ctr_low, false);

	ret |= dwmac5_est_write(ioaddr, CTR_HIGH, total_ctr, false);

	if (ret)

		return ret;



	ctrl = readl(ioaddr + MTL_EST_CONTROL);

	ctrl &= ~PTOV;

	ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;

	if (cfg->enable)

		ctrl |= EEST | SSWL;

	else

		ctrl &= ~EEST;



	writel(ctrl, ioaddr + MTL_EST_CONTROL);

	return 0;

}



void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,

			  bool enable)

{

	u32 value;



	if (!enable) {

		value = readl(ioaddr + MAC_FPE_CTRL_STS);



		value &= ~EFPE;



		writel(value, ioaddr + MAC_FPE_CTRL_STS);

	}



	value = readl(ioaddr + GMAC_RXQ_CTRL1);

	value &= ~GMAC_RXQCTRL_FPRQ;

	value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;

	writel(value, ioaddr + GMAC_RXQ_CTRL1);



	value = readl(ioaddr + MAC_FPE_CTRL_STS);

	value |= EFPE;

	writel(value, ioaddr + MAC_FPE_CTRL_STS);

}

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