drm/amdgpu/gfx9: add enable/disable funcs for cp power gating (3a6cc477) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+25 −0

Original line number	Diff line number	Diff line
		@@ -1941,6 +1941,25 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad
		}
		}

		static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
		bool enable)
		{
		uint32_t data = 0;
		uint32_t default_data = 0;

		default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

		if (enable == true) {
		data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
		if(default_data != data)
		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
		} else {
		data \|= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
		if(default_data != data)
		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
		}
		}

		static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
		{
		if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG \|
		@@ -1957,6 +1976,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
		WREG32(mmRLC_JUMP_TABLE_RESTORE,
		adev->gfx.rlc.cp_table_gpu_addr >> 8);
		gfx_v9_0_init_gfx_power_gating(adev);

		if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
		gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
		gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
		@@ -1964,6 +1984,11 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
		gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
		gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
		}

		if (adev->pg_flags & AMD_PG_SUPPORT_CP)
		gfx_v9_0_enable_cp_power_gating(adev, true);
		else
		gfx_v9_0_enable_cp_power_gating(adev, false);
		}
		}
		}