Commit 3a647c1d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  The largest single change here this time around is the Tegra
  iommu/memory controller driver, which gets updated to the new iommu DT
  binding.  More drivers like this are likely to follow for the
  following merge window, but we should be able to do those through the
  iommu maintainer.

  Other notable changes are:
   - reset controller drivers from the reset maintainer (socfpga, sti,
     berlin)
   - fixes for the keystone navigator driver merged last time
   - at91 rtc driver changes related to the at91 cleanups
   - ARM perf driver changes from Will Deacon
   - updates for the brcmstb_gisb driver"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
  clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
  clocksource: arch_timer: Fix code to use physical timers when requested
  memory: Add NVIDIA Tegra memory controller support
  bus: brcmstb_gisb: Add register offset tables for older chips
  bus: brcmstb_gisb: Look up register offsets in a table
  bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses
  bus: brcmstb_gisb: Make the driver buildable on MIPS
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  serial: samsung: Fix serial config dependencies for exynos7
  bus: brcmstb_gisb: resolve section mismatch
  ARM: common: edma: edma_pm_resume may be unused
  ARM: common: edma: add suspend resume hook
  powerpc/iommu: Rename iommu_[un]map_sg functions
  rtc: at91sam9: add DT bindings documentation
  rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK
  ARM: at91: add clk_lookup entry for RTT devices
  rtc: at91sam9: rework the Kconfig description
  ...
parents 6cd94d5e 5db45002

Documentation/devicetree/bindings/arm/arch_timer.txt

+8 −0
Original line number Diff line number Diff line
@@ -22,6 +22,14 @@ to deliver its interrupts via SPIs. 
- always-on : a boolean property. If present, the timer is powered through an

  always-on power domain, therefore it never loses context.



** Optional properties:



- arm,cpu-registers-not-fw-configured : Firmware does not initialize

  any of the generic timer CPU registers, which contain their

  architecturally-defined reset values. Only supported for 32-bit

  systems which follow the ARMv7 architected reset values.





Example:



	timer {

Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt

+5 −1
Original line number Diff line number Diff line
@@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller 


Required properties:



- compatible: should be "brcm,gisb-arb"

- compatible:

    "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips

    "brcm,bcm7435-gisb-arb" for newer 40nm chips

    "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips

    "brcm,bcm7038-gisb-arb" for 130nm chips

- reg: specifies the base physical address and size of the registers

- interrupt-parent: specifies the phandle to the parent interrupt controller

  this arbiter gets interrupt line from

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
NVIDIA Tegra Memory Controller device tree bindings

===================================================



Required properties:

- compatible: Should be "nvidia,tegra<chip>-mc"

- reg: Physical base address and length of the controller's registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts: The interrupt outputs from the controller.

- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines

  the SWGROUP of the master.



This device implements an IOMMU that complies with the generic IOMMU binding.

See ../iommu/iommu.txt for details.



Example:

--------



	mc: memory-controller@0,70019000 {

		compatible = "nvidia,tegra124-mc";

		reg = <0x0 0x70019000 0x0 0x1000>;

		clocks = <&tegra_car TEGRA124_CLK_MC>;

		clock-names = "mc";



		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;



		#iommu-cells = <1>;

	};



	sdhci@0,700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		...

		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;

	};

Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt

0 → 100644
+42 −0
Original line number Diff line number Diff line 
STMicroelectronics STi family Sysconfig Picophy SoftReset Controller

=============================================================================



This binding describes a reset controller device that is used to enable and

disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in

the STi family SoC system configuration registers.



The actual action taken when softreset is asserted is hardware dependent.

However, when asserted it may not be possible to access the hardware's

registers and after an assert/deassert sequence the hardware's previous state

may no longer be valid.



Please refer to Documentation/devicetree/bindings/reset/reset.txt

for common reset controller binding usage.



Required properties:

- compatible: Should be "st,stih407-picophyreset"

- #reset-cells: 1, see below



Example:



	picophyreset: picophyreset-controller {

		compatible = "st,stih407-picophyreset";

		#reset-cells = <1>;

	};



Specifying picophyreset control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the picophyreset device node and an

index specifying which channel to use, as described in

Documentation/devicetree/bindings/reset/reset.txt.



Example:



	usb2_picophy0: usbpicophy@0 {

		resets = <&picophyreset STIH407_PICOPHY0_RESET>;

	};



Macro definitions for the supported reset channels can be found in:

include/dt-bindings/reset-controller/stih407-resets.h

Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt

0 → 100644
+23 −0
Original line number Diff line number Diff line 
Atmel AT91SAM9260 Real Time Timer



Required properties:

- compatible: should be: "atmel,at91sam9260-rtt"

- reg: should encode the memory region of the RTT controller

- interrupts: rtt alarm/event interrupt

- clocks: should contain the 32 KHz slow clk that will drive the RTT block.

- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store

	the time base when the RTT is used as an RTC.

	The first cell should point to the GPBR node and the second one

	encode the offset within the GPBR block (or in other words, the

	GPBR register used to store the time base).





Example:



rtt@fffffd20 {

	compatible = "atmel,at91sam9260-rtt";

	reg = <0xfffffd20 0x10>;

	interrupts = <1 4 7>;

	clocks = <&clk32k>;

	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE