Commit 3a36044e authored by Alexandre Mergnat's avatar Alexandre Mergnat Committed by Jerome Brunet
Browse files

clk: meson: clk-regmap: migrate to new parent description method 



This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 4b5b85c0

drivers/clk/meson/axg.c

+3 −0
Original line number Diff line number Diff line
@@ -1096,6 +1096,9 @@ static struct clk_regmap axg_gen_clk = { 
	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)



/* Everything Else (EE) domain gates */

static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);

static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);

drivers/clk/meson/clk-regmap.h

+6 −6
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) 
extern const struct clk_ops clk_regmap_mux_ops;

extern const struct clk_ops clk_regmap_mux_ro_ops;



#define __MESON_GATE(_name, _reg, _bit, _ops)				\

#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname)			\

struct clk_regmap _name = {						\

	.data = &(struct clk_regmap_gate_data){				\

		.offset = (_reg),					\
@@ -120,15 +120,15 @@ struct clk_regmap _name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name = #_name,						\

		.ops = _ops,						\

		.parent_names = (const char *[]){ "clk81" },		\

		.parent_hws = (const struct clk_hw *[]) { _pname },	\

		.num_parents = 1,					\

		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\

	},								\

}



#define MESON_GATE(_name, _reg, _bit)	\

	__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops)

#define MESON_PCLK(_name, _reg, _bit, _pname)	\

	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)



#define MESON_GATE_RO(_name, _reg, _bit)	\

	__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops)

#define MESON_PCLK_RO(_name, _reg, _bit, _pname)	\

	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)

#endif /* __CLK_REGMAP_H */

drivers/clk/meson/g12a.c

+6 −0
Original line number Diff line number Diff line
@@ -3325,6 +3325,12 @@ static struct clk_regmap g12a_ts = { 
	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)



#define MESON_GATE_RO(_name, _reg, _bit) \

	MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)



/* Everything Else (EE) domain gates */

static MESON_GATE(g12a_ddr,			HHI_GCLK_MPEG0,	0);

static MESON_GATE(g12a_dos,			HHI_GCLK_MPEG0,	1);

drivers/clk/meson/gxbb.c

+3 −0
Original line number Diff line number Diff line
@@ -2587,6 +2587,9 @@ static struct clk_regmap gxbb_gen_clk = { 
	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)



/* Everything Else (EE) domain gates */

static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);

static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);

drivers/clk/meson/meson8b.c

+3 −0
Original line number Diff line number Diff line
@@ -2564,6 +2564,9 @@ static struct clk_regmap meson8b_cts_i958 = { 
	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)



/* Everything Else (EE) domain gates */



static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);

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