Commit 3a2b37b0 authored Mar 21, 2019 by Evan Green Committed by Andy Gross May 29, 2019

arm64: dts: msm8996: Add UFS PHY reset controller



Add the reset controller for the UFS controller, and wire it up
so that the UFS PHY can initialize itself without relying on
implicit sequencing between the two drivers.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>

parent a188339c

arch/arm64/boot/dts/qcom/msm8996.dtsi

+3 −1

Original line number	Diff line number	Diff line
		@@ -854,10 +854,11 @@
		clock-names = "ref_clk_src", "ref_clk";
		clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
		<&gcc GCC_UFS_CLKREF_CLK>;
		resets = <&ufshc 0>;
		status = "disabled";
		};

		ufshc@624000 {
		ufshc: ufshc@624000 {
		compatible = "qcom,ufshc";
		reg = <0x624000 0x2500>;
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		@@ -913,6 +914,7 @@
		<0 0>;

		lanes-per-direction = <1>;
		#reset-cells = <1>;
		status = "disabled";

		ufs_variant {

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