Commit 3a25e46c authored by Julien Grall's avatar Julien Grall Committed by Catalin Marinas
Browse files

docs/arm64: elf_hwcaps: sort the HWCAP{, 2} documentation by ascending value 



Part of the hardware capabilities documented in elf_hwcap.rst are
ordered following the definition in the header
arch/arm64/include/uapi/asm/hwcap.h but others seems to be documented
in random order.

To make easier to match against the definition in the header, they are
now sorted in the same order as they are defined in header. I.e.,
HWCAP first by ascending value, and then HWCAP2 in the similar fashion.

Acked-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarJulien Grall <julien.grall@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 4f5cafb5

Documentation/arm64/elf_hwcaps.rst

+32 −32
Original line number Diff line number Diff line
@@ -119,10 +119,6 @@ HWCAP_LRCPC 
HWCAP_DCPOP

    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.



HWCAP2_DCPODP



    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP_SHA3

    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
@@ -141,30 +137,6 @@ HWCAP_SHA512 
HWCAP_SVE

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.



HWCAP2_SVE2



    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.



HWCAP2_SVEAES



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM



    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3



    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4



    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP_ASIMDFHM

   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
@@ -180,10 +152,6 @@ HWCAP_ILRCPC 
HWCAP_FLAGM

    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.



HWCAP2_FLAGM2



    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.



HWCAP_SSBS

    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
@@ -197,6 +165,38 @@ HWCAP_PACG 
    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by

    Documentation/arm64/pointer-authentication.rst.



HWCAP2_DCPODP



    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP2_SVE2



    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.



HWCAP2_SVEAES



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM



    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3



    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4



    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP2_FLAGM2



    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.



HWCAP2_FRINT



    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.

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