[PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fix (3a1e5015) · Commits · 戴 / test

Patch from George G. Davis As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz , the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups. Signed-off-by: George G. Davis Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mm/abort-ev6.S

+16 −0

Original line number	Diff line number	Diff line
		#include <linux/linkage.h>
		#include <asm/assembler.h>
		#include "abort-macro.S"
		/*
		* Function: v6_early_abort
		*
		@@ -13,11 +14,26 @@
		* : sp = pointer to registers
		*
		* Purpose : obtain information about current aborted instruction.
		* Note: we read user space. This means we might cause a data
		* abort here if the I-TLB and D-TLB aren't seeing the same
		* picture. Unfortunately, this does happen. We live with it.
		*/
		.align 5
		ENTRY(v6_early_abort)
		mrc p15, 0, r1, c5, c0, 0 @ get FSR
		mrc p15, 0, r0, c6, c0, 0 @ get FAR
		/*
		* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
		* The test below covers all the write situations, including Java bytecodes
		*/
		bic r1, r1, #1 << 11 \| 1 << 10 @ clear bits 11 and 10 of FSR
		tst r3, #PSR_J_BIT @ Java?
		movne pc, lr
		do_thumb_abort
		ldreq r3, [r2] @ read aborted ARM instruction
		do_ldrd_abort
		tst r3, #1 << 20 @ L = 0 -> write
		orreq r1, r1, #1 << 11 @ yes.
		mov pc, lr

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