powerpc: Move SPEFSCR defines to common header (39fd0932) · Commits · 戴 / test

arch/powerpc/include/asm/reg.h

+30 −0

Original line number	Diff line number	Diff line
		@@ -143,6 +143,36 @@
		#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
		#define FPSCR_RN 0x00000003 /* FPU rounding control */

		/* Bit definitions for SPEFSCR. */
		#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
		#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
		#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
		#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
		#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
		#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
		#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
		#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
		#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
		#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
		#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
		#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
		#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
		#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
		#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
		#define SPEFSCR_OV 0x00004000 /* Integer overflow */
		#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
		#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
		#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
		#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
		#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
		#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
		#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
		#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
		#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
		#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
		#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
		#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */

		/* Special Purpose Registers (SPRNs)*/
		#define SPRN_CTR 0x009 /* Count Register */
		#define SPRN_DSCR 0x11

arch/powerpc/include/asm/reg_booke.h

+0 −30

Original line number	Diff line number	Diff line
		@@ -423,36 +423,6 @@
		#define SGR_NORMAL 0 /* Speculative fetching allowed. */
		#define SGR_GUARDED 1 /* Speculative fetching disallowed. */

		/* Bit definitions for SPEFSCR. */
		#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
		#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
		#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
		#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
		#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
		#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
		#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
		#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
		#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
		#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
		#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
		#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
		#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
		#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
		#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
		#define SPEFSCR_OV 0x00004000 /* Integer overflow */
		#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
		#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
		#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
		#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
		#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
		#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
		#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
		#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
		#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
		#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
		#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
		#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */

		/*
		* The IBM-403 is an even more odd special case, as it is much
		* older than the IBM-405 series. We put these down here incase someone

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