drm/i915: Split struct intel_context definition to its own header (39e2f501) · Commits · 戴 / test

drivers/gpu/drm/i915/Makefile

+9 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,15 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o
		i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
		i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o

		# Test the headers are compilable as standalone units
		i915-$(CONFIG_DRM_I915_WERROR) += \
		test_i915_active_types_standalone.o \
		test_i915_gem_context_types_standalone.o \
		test_i915_timeline_types_standalone.o \
		test_intel_context_types_standalone.o \
		test_intel_engine_types_standalone.o \
		test_intel_workarounds_types_standalone.o

		# GEM code
		i915-y += \
		i915_active.o \

drivers/gpu/drm/i915/i915_gem_context.h

+2 −236

Original line number	Diff line number	Diff line
		@@ -25,218 +25,17 @@
		#ifndef __I915_GEM_CONTEXT_H__
		#define __I915_GEM_CONTEXT_H__

		#include <linux/bitops.h>
		#include <linux/list.h>
		#include <linux/radix-tree.h>
		#include "i915_gem_context_types.h"

		#include "i915_gem.h"
		#include "i915_scheduler.h"
		#include "intel_context.h"
		#include "intel_device_info.h"
		#include "intel_ringbuffer.h"

		struct pid;

		struct drm_device;
		struct drm_file;

		struct drm_i915_private;
		struct drm_i915_file_private;
		struct i915_hw_ppgtt;
		struct i915_request;
		struct i915_vma;
		struct intel_ring;

		#define DEFAULT_CONTEXT_HANDLE 0

		struct intel_context;

		struct intel_context_ops {
		void (unpin)(struct intel_context ce);
		void (destroy)(struct intel_context ce);
		};

		/*
		* Powergating configuration for a particular (context,engine).
		*/
		struct intel_sseu {
		u8 slice_mask;
		u8 subslice_mask;
		u8 min_eus_per_subslice;
		u8 max_eus_per_subslice;
		};

		/**
		* struct i915_gem_context - client state
		*
		* The struct i915_gem_context represents the combined view of the driver and
		* logical hardware state for a particular client.
		*/
		struct i915_gem_context {
		/** i915: i915 device backpointer */
		struct drm_i915_private *i915;

		/** file_priv: owning file descriptor */
		struct drm_i915_file_private *file_priv;

		/**
		* @ppgtt: unique address space (GTT)
		*
		* In full-ppgtt mode, each context has its own address space ensuring
		* complete seperation of one client from all others.
		*
		* In other modes, this is a NULL pointer with the expectation that
		* the caller uses the shared global GTT.
		*/
		struct i915_hw_ppgtt *ppgtt;

		/**
		* @pid: process id of creator
		*
		* Note that who created the context may not be the principle user,
		* as the context may be shared across a local socket. However,
		* that should only affect the default context, all contexts created
		* explicitly by the client are expected to be isolated.
		*/
		struct pid *pid;

		/**
		* @name: arbitrary name
		*
		* A name is constructed for the context from the creator's process
		* name, pid and user handle in order to uniquely identify the
		* context in messages.
		*/
		const char *name;

		/** link: place with &drm_i915_private.context_list */
		struct list_head link;
		struct llist_node free_link;

		/**
		* @ref: reference count
		*
		* A reference to a context is held by both the client who created it
		* and on each request submitted to the hardware using the request
		* (to ensure the hardware has access to the state until it has
		* finished all pending writes). See i915_gem_context_get() and
		* i915_gem_context_put() for access.
		*/
		struct kref ref;

		/**
		* @rcu: rcu_head for deferred freeing.
		*/
		struct rcu_head rcu;

		/**
		* @user_flags: small set of booleans controlled by the user
		*/
		unsigned long user_flags;
		#define UCONTEXT_NO_ZEROMAP 0
		#define UCONTEXT_NO_ERROR_CAPTURE 1
		#define UCONTEXT_BANNABLE 2
		#define UCONTEXT_RECOVERABLE 3

		/**
		* @flags: small set of booleans
		*/
		unsigned long flags;
		#define CONTEXT_BANNED 0
		#define CONTEXT_CLOSED 1
		#define CONTEXT_FORCE_SINGLE_SUBMISSION 2

		/**
		* @hw_id: - unique identifier for the context
		*
		* The hardware needs to uniquely identify the context for a few
		* functions like fault reporting, PASID, scheduling. The
		* &drm_i915_private.context_hw_ida is used to assign a unqiue
		* id for the lifetime of the context.
		*
		* @hw_id_pin_count: - number of times this context had been pinned
		* for use (should be, at most, once per engine).
		*
		* @hw_id_link: - all contexts with an assigned id are tracked
		* for possible repossession.
		*/
		unsigned int hw_id;
		atomic_t hw_id_pin_count;
		struct list_head hw_id_link;

		struct list_head active_engines;
		struct mutex mutex;

		/**
		* @user_handle: userspace identifier
		*
		* A unique per-file identifier is generated from
		* &drm_i915_file_private.contexts.
		*/
		u32 user_handle;

		struct i915_sched_attr sched;

		/** engine: per-engine logical HW state */
		struct intel_context {
		struct i915_gem_context *gem_context;
		struct intel_engine_cs *engine;
		struct intel_engine_cs *active;
		struct list_head active_link;
		struct list_head signal_link;
		struct list_head signals;
		struct i915_vma *state;
		struct intel_ring *ring;
		u32 *lrc_reg_state;
		u64 lrc_desc;
		int pin_count;

		/**
		* active_tracker: Active tracker for the external rq activity
		* on this intel_context object.
		*/
		struct i915_active_request active_tracker;

		const struct intel_context_ops *ops;

		/** sseu: Control eu/slice partitioning */
		struct intel_sseu sseu;
		} __engine[I915_NUM_ENGINES];

		/** ring_size: size for allocating the per-engine ring buffer */
		u32 ring_size;
		/** desc_template: invariant fields for the HW context descriptor */
		u32 desc_template;

		/** guilty_count: How many times this context has caused a GPU hang. */
		atomic_t guilty_count;
		/**
		* @active_count: How many times this context was active during a GPU
		* hang, but did not cause it.
		*/
		atomic_t active_count;

		/**
		* @hang_timestamp: The last time(s) this context caused a GPU hang
		*/
		unsigned long hang_timestamp[2];
		#define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) /* 3 hangs within 120s? Banned! */

		/** remap_slice: Bitmask of cache lines that need remapping */
		u8 remap_slice;

		/** handles_vma: rbtree to look up our context specific obj/vma for
		* the user handle. (user handles are per fd, but the binding is
		* per vm, which may be one per context or shared with the global GTT)
		*/
		struct radix_tree_root handles_vma;

		/** handles_list: reverse list of all the rbtree entries in use for
		* this context, which allows us to free all the allocations on
		* context close.
		*/
		struct list_head handles_list;
		};

		static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx)
		{
		return test_bit(CONTEXT_CLOSED, &ctx->flags);
		@@ -338,35 +137,6 @@ static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
		return !ctx->file_priv;
		}

		static inline struct intel_context *
		to_intel_context(struct i915_gem_context *ctx,
		const struct intel_engine_cs *engine)
		{
		return &ctx->__engine[engine->id];
		}

		static inline struct intel_context *
		intel_context_pin(struct i915_gem_context ctx, struct intel_engine_cs engine)
		{
		return engine->context_pin(engine, ctx);
		}

		static inline void __intel_context_pin(struct intel_context *ce)
		{
		GEM_BUG_ON(!ce->pin_count);
		ce->pin_count++;
		}

		static inline void intel_context_unpin(struct intel_context *ce)
		{
		GEM_BUG_ON(!ce->pin_count);
		if (--ce->pin_count)
		return;

		GEM_BUG_ON(!ce->ops);
		ce->ops->unpin(ce);
		}

		/* i915_gem_context.c */
		int __must_check i915_gem_contexts_init(struct drm_i915_private *dev_priv);
		void i915_gem_contexts_lost(struct drm_i915_private *dev_priv);
		@@ -410,10 +180,6 @@ static inline void i915_gem_context_put(struct i915_gem_context *ctx)
		kref_put(&ctx->ref, i915_gem_context_release);
		}

		void intel_context_init(struct intel_context *ce,
		struct i915_gem_context *ctx,
		struct intel_engine_cs *engine);

		struct i915_lut_handle *i915_lut_handle_alloc(void);
		void i915_lut_handle_free(struct i915_lut_handle *lut);

drivers/gpu/drm/i915/i915_gem_context_types.h

0 → 100644

+181 −0

Original line number	Diff line number	Diff line
		/*
		* SPDX-License-Identifier: MIT
		*
		* Copyright © 2019 Intel Corporation
		*/

		#ifndef __I915_GEM_CONTEXT_TYPES_H__
		#define __I915_GEM_CONTEXT_TYPES_H__

		#include <linux/atomic.h>
		#include <linux/list.h>
		#include <linux/llist.h>
		#include <linux/kref.h>
		#include <linux/mutex.h>
		#include <linux/radix-tree.h>
		#include <linux/rcupdate.h>
		#include <linux/types.h>

		#include "i915_gem.h" /* I915_NUM_ENGINES */
		#include "i915_scheduler.h"
		#include "intel_context_types.h"

		struct pid;

		struct drm_i915_private;
		struct drm_i915_file_private;
		struct i915_hw_ppgtt;
		struct i915_timeline;
		struct intel_ring;

		/**
		* struct i915_gem_context - client state
		*
		* The struct i915_gem_context represents the combined view of the driver and
		* logical hardware state for a particular client.
		*/
		struct i915_gem_context {
		/** i915: i915 device backpointer */
		struct drm_i915_private *i915;

		/** file_priv: owning file descriptor */
		struct drm_i915_file_private *file_priv;

		/**
		* @ppgtt: unique address space (GTT)
		*
		* In full-ppgtt mode, each context has its own address space ensuring
		* complete seperation of one client from all others.
		*
		* In other modes, this is a NULL pointer with the expectation that
		* the caller uses the shared global GTT.
		*/
		struct i915_hw_ppgtt *ppgtt;

		/**
		* @pid: process id of creator
		*
		* Note that who created the context may not be the principle user,
		* as the context may be shared across a local socket. However,
		* that should only affect the default context, all contexts created
		* explicitly by the client are expected to be isolated.
		*/
		struct pid *pid;

		/**
		* @name: arbitrary name
		*
		* A name is constructed for the context from the creator's process
		* name, pid and user handle in order to uniquely identify the
		* context in messages.
		*/
		const char *name;

		/** link: place with &drm_i915_private.context_list */
		struct list_head link;
		struct llist_node free_link;

		/**
		* @ref: reference count
		*
		* A reference to a context is held by both the client who created it
		* and on each request submitted to the hardware using the request
		* (to ensure the hardware has access to the state until it has
		* finished all pending writes). See i915_gem_context_get() and
		* i915_gem_context_put() for access.
		*/
		struct kref ref;

		/**
		* @rcu: rcu_head for deferred freeing.
		*/
		struct rcu_head rcu;

		/**
		* @user_flags: small set of booleans controlled by the user
		*/
		unsigned long user_flags;
		#define UCONTEXT_NO_ZEROMAP 0
		#define UCONTEXT_NO_ERROR_CAPTURE 1
		#define UCONTEXT_BANNABLE 2
		#define UCONTEXT_RECOVERABLE 3

		/**
		* @flags: small set of booleans
		*/
		unsigned long flags;
		#define CONTEXT_BANNED 0
		#define CONTEXT_CLOSED 1
		#define CONTEXT_FORCE_SINGLE_SUBMISSION 2

		/**
		* @hw_id: - unique identifier for the context
		*
		* The hardware needs to uniquely identify the context for a few
		* functions like fault reporting, PASID, scheduling. The
		* &drm_i915_private.context_hw_ida is used to assign a unqiue
		* id for the lifetime of the context.
		*
		* @hw_id_pin_count: - number of times this context had been pinned
		* for use (should be, at most, once per engine).
		*
		* @hw_id_link: - all contexts with an assigned id are tracked
		* for possible repossession.
		*/
		unsigned int hw_id;
		atomic_t hw_id_pin_count;
		struct list_head hw_id_link;

		struct list_head active_engines;
		struct mutex mutex;

		/**
		* @user_handle: userspace identifier
		*
		* A unique per-file identifier is generated from
		* &drm_i915_file_private.contexts.
		*/
		u32 user_handle;
		#define DEFAULT_CONTEXT_HANDLE 0

		struct i915_sched_attr sched;

		/** engine: per-engine logical HW state */
		struct intel_context __engine[I915_NUM_ENGINES];

		/** ring_size: size for allocating the per-engine ring buffer */
		u32 ring_size;
		/** desc_template: invariant fields for the HW context descriptor */
		u32 desc_template;

		/** guilty_count: How many times this context has caused a GPU hang. */
		atomic_t guilty_count;
		/**
		* @active_count: How many times this context was active during a GPU
		* hang, but did not cause it.
		*/
		atomic_t active_count;

		/**
		* @hang_timestamp: The last time(s) this context caused a GPU hang
		*/
		unsigned long hang_timestamp[2];
		#define CONTEXT_FAST_HANG_JIFFIES (120 * HZ) /* 3 hangs within 120s? Banned! */

		/** remap_slice: Bitmask of cache lines that need remapping */
		u8 remap_slice;

		/** handles_vma: rbtree to look up our context specific obj/vma for
		* the user handle. (user handles are per fd, but the binding is
		* per vm, which may be one per context or shared with the global GTT)
		*/
		struct radix_tree_root handles_vma;

		/** handles_list: reverse list of all the rbtree entries in use for
		* this context, which allows us to free all the allocations on
		* context close.
		*/
		struct list_head handles_list;
		};

		#endif /* __I915_GEM_CONTEXT_TYPES_H__ */

drivers/gpu/drm/i915/i915_timeline.h

+2 −68

Original line number	Diff line number	Diff line
		@@ -25,76 +25,10 @@
		#ifndef I915_TIMELINE_H
		#define I915_TIMELINE_H

		#include <linux/list.h>
		#include <linux/kref.h>
		#include <linux/lockdep.h>

		#include "i915_active.h"
		#include "i915_request.h"
		#include "i915_syncmap.h"
		#include "i915_utils.h"

		struct i915_vma;
		struct i915_timeline_cacheline;

		struct i915_timeline {
		u64 fence_context;
		u32 seqno;

		spinlock_t lock;
		#define TIMELINE_CLIENT 0 /* default subclass */
		#define TIMELINE_ENGINE 1

		struct mutex mutex; /* protects the flow of requests */

		unsigned int pin_count;
		const u32 *hwsp_seqno;
		struct i915_vma *hwsp_ggtt;
		u32 hwsp_offset;

		struct i915_timeline_cacheline *hwsp_cacheline;

		bool has_initial_breadcrumb;

		/**
		* List of breadcrumbs associated with GPU requests currently
		* outstanding.
		*/
		struct list_head requests;

		/* Contains an RCU guarded pointer to the last request. No reference is
		* held to the request, users must carefully acquire a reference to
		* the request using i915_active_request_get_request_rcu(), or hold the
		* struct_mutex.
		*/
		struct i915_active_request last_request;

		/**
		* We track the most recent seqno that we wait on in every context so
		* that we only have to emit a new await and dependency on a more
		* recent sync point. As the contexts may be executed out-of-order, we
		* have to track each individually and can not rely on an absolute
		* global_seqno. When we know that all tracked fences are completed
		* (i.e. when the driver is idle), we know that the syncmap is
		* redundant and we can discard it without loss of generality.
		*/
		struct i915_syncmap *sync;

		/**
		* Barrier provides the ability to serialize ordering between different
		* timelines.
		*
		* Users can call i915_timeline_set_barrier which will make all
		* subsequent submissions to this timeline be executed only after the
		* barrier has been completed.
		*/
		struct i915_active_request barrier;

		struct list_head link;
		const char *name;
		struct drm_i915_private *i915;

		struct kref kref;
		};
		#include "i915_timeline_types.h"

		int i915_timeline_init(struct drm_i915_private *i915,
		struct i915_timeline *tl,

drivers/gpu/drm/i915/i915_timeline_types.h

0 → 100644

+80 −0

Original line number	Diff line number	Diff line
		/*
		* SPDX-License-Identifier: MIT
		*
		* Copyright © 2016 Intel Corporation
		*/

		#ifndef __I915_TIMELINE_TYPES_H__
		#define __I915_TIMELINE_TYPES_H__

		#include <linux/list.h>
		#include <linux/kref.h>
		#include <linux/types.h>

		#include "i915_active.h"

		struct drm_i915_private;
		struct i915_vma;
		struct i915_timeline_cacheline;
		struct i915_syncmap;

		struct i915_timeline {
		u64 fence_context;
		u32 seqno;

		spinlock_t lock;
		#define TIMELINE_CLIENT 0 /* default subclass */
		#define TIMELINE_ENGINE 1
		struct mutex mutex; /* protects the flow of requests */

		unsigned int pin_count;
		const u32 *hwsp_seqno;
		struct i915_vma *hwsp_ggtt;
		u32 hwsp_offset;

		struct i915_timeline_cacheline *hwsp_cacheline;

		bool has_initial_breadcrumb;

		/**
		* List of breadcrumbs associated with GPU requests currently
		* outstanding.
		*/
		struct list_head requests;

		/* Contains an RCU guarded pointer to the last request. No reference is
		* held to the request, users must carefully acquire a reference to
		* the request using i915_active_request_get_request_rcu(), or hold the
		* struct_mutex.
		*/
		struct i915_active_request last_request;

		/**
		* We track the most recent seqno that we wait on in every context so
		* that we only have to emit a new await and dependency on a more
		* recent sync point. As the contexts may be executed out-of-order, we
		* have to track each individually and can not rely on an absolute
		* global_seqno. When we know that all tracked fences are completed
		* (i.e. when the driver is idle), we know that the syncmap is
		* redundant and we can discard it without loss of generality.
		*/
		struct i915_syncmap *sync;

		/**
		* Barrier provides the ability to serialize ordering between different
		* timelines.
		*
		* Users can call i915_timeline_set_barrier which will make all
		* subsequent submissions to this timeline be executed only after the
		* barrier has been completed.
		*/
		struct i915_active_request barrier;

		struct list_head link;
		const char *name;
		struct drm_i915_private *i915;

		struct kref kref;
		};

		#endif /* __I915_TIMELINE_TYPES_H__ */

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