drm/amd/display: fix dcn-specific clk_mgr init_clocks (39bdac36) · Commits · 戴 / test

[Why] underflow seen on certain monitor setups caused by making dcnxx_init_hw generic [How] by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr memset in an else statement so both memsets don't get set Signed-off-by:

Martin Leung <martin.leung@amd.com> Reviewed-by:

Anthony Koo <Anthony.Koo@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,11 @@
		#include "rv1_clk_mgr_vbios_smu.h"
		#include "rv1_clk_mgr_clk.h"

		void rv1_init_clocks(struct clk_mgr *clk_mgr)
		{
		memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
		}

		static int rv1_determine_dppclk_threshold(struct clk_mgr_internal clk_mgr, struct dc_clocks new_clocks)
		{
		bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
		@@ -232,6 +237,7 @@ static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
		}

		static struct clk_mgr_funcs rv1_clk_funcs = {
		.init_clocks = rv1_init_clocks,
		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
		.update_clocks = rv1_update_clocks,
		.enable_pme_wa = rv1_enable_pme_wa,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -1291,8 +1291,6 @@ static void dcn10_init_hw(struct dc *dc)
		}

		dc->hwss.enable_power_gating_plane(dc->hwseq, true);

		memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
		}

		static void dcn10_reset_hw_ctx_wrap(

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