Commit 39a1af76 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/virtualization' 

  - Remove unused xen_register_pirq() parameter (Wei Liu)

  - Quirk AMD Matisse HD Audio & USB 3.0 devices where FLR hangs the device
    (Marcos Scriven)

  - Quirk AMD Starship USB 3.0 device where FLR doesn't seem to work (Kevin
    Buettner)

  - Add ACS quirk for Intel RCiEPs (Ashok Raj)

* pci/virtualization:
  PCI: Add ACS quirk for Intel Root Complex Integrated Endpoints
  PCI: Avoid FLR for AMD Starship USB 3.0
  PCI: Avoid FLR for AMD Matisse HD Audio & USB 3.0
  x86/PCI: Drop unused xen_register_pirq() gsi_override parameter
parents 0085090d 3247bd10

arch/x86/pci/xen.c

+6 −10
Original line number Diff line number Diff line
@@ -60,8 +60,7 @@ static int xen_pcifront_enable_irq(struct pci_dev *dev) 
}



#ifdef CONFIG_ACPI

static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,

			     bool set_pirq)

static int xen_register_pirq(u32 gsi, int triggering, bool set_pirq)

{

	int rc, pirq = -1, irq = -1;

	struct physdev_map_pirq map_irq;
@@ -94,9 +93,6 @@ static int xen_register_pirq(u32 gsi, int gsi_override, int triggering, 
		name = "ioapic-level";

	}



	if (gsi_override >= 0)

		gsi = gsi_override;



	irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);

	if (irq < 0)

		goto out;
@@ -112,12 +108,12 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi, 
	if (!xen_hvm_domain())

		return -1;



	return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,

	return xen_register_pirq(gsi, trigger,

				 false /* no mapping of GSI to PIRQ */);

}



#ifdef CONFIG_XEN_DOM0

static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)

static int xen_register_gsi(u32 gsi, int triggering, int polarity)

{

	int rc, irq;

	struct physdev_setup_gsi setup_gsi;
@@ -128,7 +124,7 @@ static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polar 
	printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",

			gsi, triggering, polarity);



	irq = xen_register_pirq(gsi, gsi_override, triggering, true);

	irq = xen_register_pirq(gsi, triggering, true);



	setup_gsi.gsi = gsi;

	setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
@@ -148,7 +144,7 @@ static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polar 
static int acpi_register_gsi_xen(struct device *dev, u32 gsi,

				 int trigger, int polarity)

{

	return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);

	return xen_register_gsi(gsi, trigger, polarity);

}

#endif

#endif
@@ -491,7 +487,7 @@ int __init pci_xen_initial_domain(void) 
		if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)

			continue;



		xen_register_pirq(irq, -1 /* no GSI override */,

		xen_register_pirq(irq,

			trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,

			true /* Map GSI to PIRQ */);

	}

drivers/pci/quirks.c

+31 −4
Original line number Diff line number Diff line
@@ -4682,6 +4682,20 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 
		PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);

}



static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)

{

	/*

	 * Intel RCiEP's are required to allow p2p only on translated

	 * addresses.  Refer to Intel VT-d specification, r3.1, sec 3.16,

	 * "Root-Complex Peer to Peer Considerations".

	 */

	if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)

		return -ENOTTY;



	return pci_acs_ctrl_enabled(acs_flags,

		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

}



static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)

{

	/*
@@ -4764,6 +4778,7 @@ static const struct pci_dev_acs_enabled { 
	/* I219 */

	{ PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },

	/* QCOM QDF2xxx root ports */

	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },

	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
@@ -5129,13 +5144,25 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 
}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);



/* FLR may cause some 82579 devices to hang */

static void quirk_intel_no_flr(struct pci_dev *dev)

/*

 * FLR may cause the following to devices to hang:

 *

 * AMD Starship/Matisse HD Audio Controller 0x1487

 * AMD Starship USB 3.0 Host Controller 0x148c

 * AMD Matisse USB 3.0 Host Controller 0x149c

 * Intel 82579LM Gigabit Ethernet Controller 0x1502

 * Intel 82579V Gigabit Ethernet Controller 0x1503

 *

 */

static void quirk_no_flr(struct pci_dev *dev)

{

	dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);



static void quirk_no_ext_tags(struct pci_dev *pdev)

{

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