Commit 399de50b authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: Refine AMD K8 write-reorder chipset test. 



Test for VIA K8T800 north bridge instead of AMD K8 HyperTransport
bridge based on new information from Andi Kleen. The AMD
HyperTransport interface is not responsible for PCI transactions
and so the re-ordering is more likely done by the VIA north bridge.
This code is subject to change if we get more information from AMD
or VIA.

PCI Express devices are excluded from doing the read flush since all
chipsets in the write_reorder list are PCI chipsets.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a232f767

drivers/net/tg3.c

+12 −11
Original line number Original line Diff line number Diff line
@@ -9284,8 +9284,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	static struct pci_device_id write_reorder_chipsets[] = {

	static struct pci_device_id write_reorder_chipsets[] = {

		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,

		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,

		             PCI_DEVICE_ID_AMD_FE_GATE_700C) },

		             PCI_DEVICE_ID_AMD_FE_GATE_700C) },

		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,

		{ PCI_DEVICE(PCI_VENDOR_ID_VIA,

		             PCI_DEVICE_ID_AMD_K8_NB) },

			     PCI_DEVICE_ID_VIA_8385_0) },

		{ },

		{ },

	};

	};

	u32 misc_ctrl_reg;

	u32 misc_ctrl_reg;
@@ -9300,15 +9300,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
		tp->tg3_flags2 |= TG3_FLG2_SUN_570X;

		tp->tg3_flags2 |= TG3_FLG2_SUN_570X;

#endif

#endif





	/* If we have an AMD 762 or K8 chipset, write

	 * reordering to the mailbox registers done by the host

	 * controller can cause major troubles.  We read back from

	 * every mailbox register write to force the writes to be

	 * posted to the chip in order.

	 */

	if (pci_dev_present(write_reorder_chipsets))

		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;



	/* Force memory write invalidate off.  If we leave it on,

	/* Force memory write invalidate off.  If we leave it on,

	 * then on 5700_BX chips we have to enable a workaround.

	 * then on 5700_BX chips we have to enable a workaround.

	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary

	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
@@ -9439,6 +9430,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)

	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)

		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;

		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;





	/* If we have an AMD 762 or VIA K8T800 chipset, write

	 * reordering to the mailbox registers done by the host

	 * controller can cause major troubles.  We read back from

	 * every mailbox register write to force the writes to be

	 * posted to the chip in order.

	 */

	if (pci_dev_present(write_reorder_chipsets) &&

	    !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))

		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&

	    tp->pci_lat_timer < 64) {

	    tp->pci_lat_timer < 64) {

		tp->pci_lat_timer = 64;

		tp->pci_lat_timer = 64;

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