Commit 3954b4e3 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Kalle Valo
Browse files

rt2x00: convert rt2x00mmio_register_read return type 



This is a semi-automated conversion to change rt2x00mmio_register_read
to return the register contents instead of passing them by value,
resulting in much better object code. The majority of the patch
was done using:

sed -i 's:\(rt2x00mmio_register_read(.*, .*\), &\(.*\));:\2 = \1);:' \
    -i 's:_rt2x00mmio_register_read:rt2x00mmio_register_read:' \
	drivers/net/wireless/ralink/rt2x00/*.c

The function itself was modified manually along with the one remaining
caller that was not covered automatically.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent aea8baa1

drivers/net/wireless/ralink/rt2x00/rt2400pci.c

+64 −64
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 
	struct rt2x00_dev *rt2x00dev = eeprom->data;

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR21);



	eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);

	eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
@@ -177,7 +177,7 @@ static u8 _rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, 
static const struct rt2x00debug rt2400pci_rt2x00debug = {

	.owner	= THIS_MODULE,

	.csr	= {

		.read		= _rt2x00mmio_register_read,

		.read		= rt2x00mmio_register_read,

		.write		= rt2x00mmio_register_write,

		.flags		= RT2X00DEBUGFS_OFFSET,

		.word_base	= CSR_REG_BASE,
@@ -212,7 +212,7 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) 
{

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);

	return rt2x00_get_field32(reg, GPIOCSR_VAL0);

}
@@ -225,7 +225,7 @@ static void rt2400pci_brightness_set(struct led_classdev *led_cdev, 
	unsigned int enabled = brightness != LED_OFF;

	u32 reg;



	rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);

	reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);



	if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)

		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
@@ -243,7 +243,7 @@ static int rt2400pci_blink_set(struct led_classdev *led_cdev, 
	    container_of(led_cdev, struct rt2x00_led, led_dev);

	u32 reg;



	rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);

	reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR);

	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);

	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);

	rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
@@ -276,7 +276,7 @@ static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, 
	 * Note that the version error will always be dropped

	 * since there is no filter for it at this time.

	 */

	rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);

	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,

			   !(filter_flags & FIF_FCSFAIL));

	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
@@ -305,14 +305,14 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, 
		 * Enable beacon config

		 */

		bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);

		rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1);

		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);

		rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);



		/*

		 * Enable synchronisation.

		 */

		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);

		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);

		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);

	}
@@ -340,35 +340,35 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {

		preamble_mask = erp->short_preamble << 3;



		rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1);

		rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);

		rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);

		rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);

		rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);

		rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);



		rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2);

		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);

		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 10));

		rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);



		rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3);

		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 20));

		rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);



		rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4);

		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 55));

		rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);



		rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5);

		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
@@ -380,23 +380,23 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 
		rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);



	if (changed & BSS_CHANGED_ERP_SLOT) {

		rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR11);

		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);

		rt2x00mmio_register_write(rt2x00dev, CSR11, reg);



		rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR18);

		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);

		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);

		rt2x00mmio_register_write(rt2x00dev, CSR18, reg);



		rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR19);

		rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);

		rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);

		rt2x00mmio_register_write(rt2x00dev, CSR19, reg);

	}



	if (changed & BSS_CHANGED_BEACON_INT) {

		rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR12);

		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,

				   erp->beacon_int * 16);

		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
@@ -505,7 +505,7 @@ static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, 
	/*

	 * Clear false CRC during channel switch.

	 */

	rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);

	rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0);

}



static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
@@ -518,7 +518,7 @@ static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 
{

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR11);

	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,

			   libconf->conf->long_frame_max_tx_count);

	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
@@ -535,7 +535,7 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, 
	u32 reg;



	if (state == STATE_SLEEP) {

		rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR20);

		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,

				   (rt2x00dev->beacon_int - 20) * 16);

		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
@@ -548,7 +548,7 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, 
		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);

		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);

	} else {

		rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR20);

		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);

		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);

	}
@@ -576,7 +576,7 @@ static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, 
{

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR11);

	rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);

	rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);

	rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
@@ -594,7 +594,7 @@ static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, 
	/*

	 * Update FCS error count from register.

	 */

	rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CNT0);

	qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);



	/*
@@ -649,12 +649,12 @@ static void rt2400pci_start_queue(struct data_queue *queue) 


	switch (queue->qid) {

	case QID_RX:

		rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);

		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);

		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);

		break;

	case QID_BEACON:

		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);

		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);

		rt2x00_set_field32(&reg, CSR14_TBCN, 1);

		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
@@ -672,17 +672,17 @@ static void rt2400pci_kick_queue(struct data_queue *queue) 


	switch (queue->qid) {

	case QID_AC_VO:

		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);

		rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);

		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);

		break;

	case QID_AC_VI:

		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);

		rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);

		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);

		break;

	case QID_ATIM:

		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);

		rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);

		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);

		break;
@@ -700,17 +700,17 @@ static void rt2400pci_stop_queue(struct data_queue *queue) 
	case QID_AC_VO:

	case QID_AC_VI:

	case QID_ATIM:

		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0);

		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);

		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);

		break;

	case QID_RX:

		rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0);

		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);

		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);

		break;

	case QID_BEACON:

		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR14);

		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);

		rt2x00_set_field32(&reg, CSR14_TBCN, 0);

		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
@@ -780,7 +780,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) 
	/*

	 * Initialize registers.

	 */

	rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2);

	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);

	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);

	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
@@ -788,36 +788,36 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) 
	rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);



	entry_priv = rt2x00dev->tx[1].entries[0].priv_data;

	rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3);

	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,

			   entry_priv->desc_dma);

	rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);



	entry_priv = rt2x00dev->tx[0].entries[0].priv_data;

	rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5);

	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,

			   entry_priv->desc_dma);

	rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);



	entry_priv = rt2x00dev->atim->entries[0].priv_data;

	rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4);

	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,

			   entry_priv->desc_dma);

	rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);



	entry_priv = rt2x00dev->bcn->entries[0].priv_data;

	rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6);

	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,

			   entry_priv->desc_dma);

	rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);



	rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1);

	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);

	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);

	rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);



	entry_priv = rt2x00dev->rx->entries[0].priv_data;

	rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2);

	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,

			   entry_priv->desc_dma);

	rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
@@ -834,18 +834,18 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);

	rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);



	rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR);

	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);

	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);

	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);

	rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);



	rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR9);

	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,

			   (rt2x00dev->rx->data_size / 128));

	rt2x00mmio_register_write(rt2x00dev, CSR9, reg);



	rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR14);

	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);

	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);

	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
@@ -858,14 +858,14 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) 


	rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);



	rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0);

	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);

	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);

	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);

	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);

	rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);



	rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3);

	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/

	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);

	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
@@ -882,24 +882,24 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) 
	rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);

	rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);



	rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2);

	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);

	rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);



	rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR);

	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);

	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);

	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);

	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);

	rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);



	rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR1);

	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);

	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);

	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);

	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);



	rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR1);

	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);

	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);

	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
@@ -909,8 +909,8 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) 
	 * These registers are cleared on read,

	 * so we may pass a useless variable to store the value.

	 */

	rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);

	rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CNT0);

	reg = rt2x00mmio_register_read(rt2x00dev, CNT4);



	return 0;

}
@@ -984,7 +984,7 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 
	 * should clear the register to assure a clean state.

	 */

	if (state == STATE_RADIO_IRQ_ON) {

		rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR7);

		rt2x00mmio_register_write(rt2x00dev, CSR7, reg);

	}
@@ -994,7 +994,7 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 
	 */

	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);



	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);

	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);

	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);

	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
@@ -1047,7 +1047,7 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, 


	put_to_sleep = (state != STATE_AWAKE);



	rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);

	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);

	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);

	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
@@ -1060,7 +1060,7 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, 
	 * device has entered the correct state.

	 */

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {

		rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);

		reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1);

		bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);

		rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);

		if (bbp_state == state && rf_state == state)
@@ -1190,7 +1190,7 @@ static void rt2400pci_write_beacon(struct queue_entry *entry, 
	 * Disable beaconing while we are reloading the beacon data,

	 * otherwise we might be sending out invalid data.

	 */

	rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR14);

	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);

	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
@@ -1330,7 +1330,7 @@ static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, 
	 */

	spin_lock_irq(&rt2x00dev->irqmask_lock);



	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);

	rt2x00_set_field32(&reg, irq_field, 0);

	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
@@ -1355,7 +1355,7 @@ static void rt2400pci_txstatus_tasklet(unsigned long data) 
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {

		spin_lock_irq(&rt2x00dev->irqmask_lock);



		rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, CSR8);

		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);

		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);

		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
@@ -1391,7 +1391,7 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) 
	 * Get the interrupt sources & saved to local variable.

	 * Write register value back to clear pending interrupts.

	 */

	rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR7);

	rt2x00mmio_register_write(rt2x00dev, CSR7, reg);



	if (!reg)
@@ -1429,7 +1429,7 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) 
	 */

	spin_lock(&rt2x00dev->irqmask_lock);



	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR8);

	reg |= mask;

	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
@@ -1450,7 +1450,7 @@ static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) 
	u16 word;

	u8 *mac;



	rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR21);



	eeprom.data = rt2x00dev;

	eeprom.register_read = rt2400pci_eepromregister_read;
@@ -1495,7 +1495,7 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) 
	 * Identify RF chipset.

	 */

	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);

	rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR0);

	rt2x00_set_chip(rt2x00dev, RT2460, value,

			rt2x00_get_field32(reg, CSR0_REVISION));
@@ -1640,7 +1640,7 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) 
	 * Enable rfkill polling by setting GPIO direction of the

	 * rfkill switch GPIO pin correctly.

	 */

	rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR);

	rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);

	rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
@@ -1702,9 +1702,9 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw, 
	u64 tsf;

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR17);

	tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;

	rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR16);

	tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);



	return tsf;
@@ -1715,7 +1715,7 @@ static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) 
	struct rt2x00_dev *rt2x00dev = hw->priv;

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, CSR15);

	return rt2x00_get_field32(reg, CSR15_BEACON_SENT);

}

drivers/net/wireless/ralink/rt2x00/rt2500pci.c

+70 −70

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ralink/rt2x00/rt2800mmio.c

+15 −15
Original line number Diff line number Diff line
@@ -331,7 +331,7 @@ static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev, 
	 * access needs locking.

	 */

	spin_lock_irq(&rt2x00dev->irqmask_lock);

	rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);

	rt2x00_set_field32(&reg, irq_field, 1);

	rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);

	spin_unlock_irq(&rt2x00dev->irqmask_lock);
@@ -376,12 +376,12 @@ void rt2800mmio_tbtt_tasklet(unsigned long data) 
		 * interval every 64 beacons by 64us to mitigate this effect.

		 */

		if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {

			rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);

			reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);

			rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,

					   (rt2x00dev->beacon_int * 16) - 1);

			rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);

		} else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {

			rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);

			reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);

			rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,

					   (rt2x00dev->beacon_int * 16));

			rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
@@ -439,7 +439,7 @@ static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev) 
	 * need to lock the kfifo.

	 */

	for (i = 0; i < rt2x00dev->tx->limit; i++) {

		rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);

		status = rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO);



		if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))

			break;
@@ -460,7 +460,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance) 
	u32 reg, mask;



	/* Read status and ACK all interrupts */

	rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);

	rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);



	if (!reg)
@@ -501,7 +501,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance) 
	 * the tasklet will reenable the appropriate interrupts.

	 */

	spin_lock(&rt2x00dev->irqmask_lock);

	rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);

	reg &= mask;

	rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);

	spin_unlock(&rt2x00dev->irqmask_lock);
@@ -521,7 +521,7 @@ void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, 
	 * should clear the register to assure a clean state.

	 */

	if (state == STATE_RADIO_IRQ_ON) {

		rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);

		rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);

	}
@@ -560,18 +560,18 @@ void rt2800mmio_start_queue(struct data_queue *queue) 


	switch (queue->qid) {

	case QID_RX:

		rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);

		rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);

		rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);

		break;

	case QID_BEACON:

		rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);

		rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);



		rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);

		rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);

		rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);

		break;
@@ -613,18 +613,18 @@ void rt2800mmio_stop_queue(struct data_queue *queue) 


	switch (queue->qid) {

	case QID_RX:

		rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);

		rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);

		rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);

		break;

	case QID_BEACON:

		rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);

		rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);



		rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);

		rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);

		rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
@@ -810,7 +810,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev) 
	/*

	 * Reset DMA indexes

	 */

	rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX);

	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);

	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);

	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -831,7 +831,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev) 
	     rt2x00_rt(rt2x00dev, RT5390) ||

	     rt2x00_rt(rt2x00dev, RT5392) ||

	     rt2x00_rt(rt2x00dev, RT5592))) {

		rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, AUX_CTRL);

		rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);

		rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);

		rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);

drivers/net/wireless/ralink/rt2x00/rt2800pci.c

+5 −5
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) 
		return;



	for (i = 0; i < 200; i++) {

		rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);

		reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);



		if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||

		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -92,7 +92,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 
	struct rt2x00_dev *rt2x00dev = eeprom->data;

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);



	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);

	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -122,7 +122,7 @@ static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 
	struct eeprom_93cx6 eeprom;

	u32 reg;



	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);

	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);



	eeprom.data = rt2x00dev;

	eeprom.register_read = rt2800pci_eepromregister_read;
@@ -325,8 +325,8 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = { 
};



static const struct rt2800_ops rt2800pci_rt2800_ops = {

	.register_read		= _rt2x00mmio_register_read,

	.register_read_lock	= _rt2x00mmio_register_read, /* same for PCI */

	.register_read		= rt2x00mmio_register_read,

	.register_read_lock	= rt2x00mmio_register_read, /* same for PCI */

	.register_write		= rt2x00mmio_register_write,

	.register_write_lock	= rt2x00mmio_register_write, /* same for PCI */

	.register_multiread	= rt2x00mmio_register_multiread,

drivers/net/wireless/ralink/rt2x00/rt2800soc.c

+2 −2
Original line number Diff line number Diff line
@@ -164,8 +164,8 @@ static const struct ieee80211_ops rt2800soc_mac80211_ops = { 
};



static const struct rt2800_ops rt2800soc_rt2800_ops = {

	.register_read		= _rt2x00mmio_register_read,

	.register_read_lock	= _rt2x00mmio_register_read, /* same for SoCs */

	.register_read		= rt2x00mmio_register_read,

	.register_read_lock	= rt2x00mmio_register_read, /* same for SoCs */

	.register_write		= rt2x00mmio_register_write,

	.register_write_lock	= rt2x00mmio_register_write, /* same for SoCs */

	.register_multiread	= rt2x00mmio_register_multiread,

CRA Git | Maintained and supported by SUSTech CRA and CCSE