drm/i915/workarounds: convert to drm_device based logging macros. (394ad36c) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_workarounds.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -837,7 +837,7 @@ wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal)
		intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
		GEN10_L3BANK_MASK;

		DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
		drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse);
		l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT \| l3_fuse);
		} else {
		l3_en = ~0;
		@@ -846,7 +846,8 @@ wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal)
		slice = fls(sseu->slice_mask) - 1;
		subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
		if (!subslice) {
		DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
		drm_warn(&i915->drm,
		"No common index found between subslice mask %x and L3 bank mask %x!\n",
		intel_sseu_get_subslices(sseu, slice), l3_en);
		subslice = fls(l3_en);
		drm_WARN_ON(&i915->drm, !subslice);
		@@ -861,7 +862,7 @@ wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal)
		mcr_mask = GEN8_MCR_SLICE_MASK \| GEN8_MCR_SUBSLICE_MASK;
		}

		DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
		drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);

		wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
		}