drm/amd/display: add AUX and I2C for DCN2 (38e71289) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,16 @@
		#include "i2caux_interface.h"
		#include "inc/hw/aux_engine.h"

		#ifdef CONFIG_DRM_AMD_DC_DCN2_0
		#define AUX_COMMON_REG_LIST0(id)\
		SRI(AUX_CONTROL, DP_AUX, id), \
		SRI(AUX_ARB_CONTROL, DP_AUX, id), \
		SRI(AUX_SW_DATA, DP_AUX, id), \
		SRI(AUX_SW_CONTROL, DP_AUX, id), \
		SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
		SRI(AUX_SW_STATUS, DP_AUX, id)
		#endif

		#define AUX_COMMON_REG_LIST(id)\
		SRI(AUX_CONTROL, DP_AUX, id), \
		SRI(AUX_ARB_CONTROL, DP_AUX, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

+32 −0

Original line number	Diff line number	Diff line
		@@ -303,6 +303,10 @@ static bool setup_engine(
		struct dce_i2c_hw *dce_i2c_hw)
		{
		uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		uint32_t reset_length = 0;
		#endif

		/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
		REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);

		@@ -323,6 +327,14 @@ static bool setup_engine(
		REG_UPDATE_N(SETUP, 2,
		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		} else {
		reset_length = dce_i2c_hw->send_reset_length;
		REG_UPDATE_N(SETUP, 3,
		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
		#endif
		}
		/* Program HW priority
		* set to High - interrupt software I2C at any time
		@@ -698,3 +710,23 @@ void dcn1_i2c_hw_construct(
		dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
		}

		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		void dcn2_i2c_hw_construct(
		struct dce_i2c_hw *dce_i2c_hw,
		struct dc_context *ctx,
		uint32_t engine_id,
		const struct dce_i2c_registers *regs,
		const struct dce_i2c_shift *shifts,
		const struct dce_i2c_mask *masks)
		{
		dcn1_i2c_hw_construct(dce_i2c_hw,
		ctx,
		engine_id,
		regs,
		shifts,
		masks);
		dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9;
		if (ctx->dc->debug.scl_reset_length10)
		dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
		}
		#endif

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

+22 −0

Original line number	Diff line number	Diff line
		@@ -177,6 +177,9 @@ struct dce_i2c_shift {
		uint8_t DC_I2C_INDEX;
		uint8_t DC_I2C_INDEX_WRITE;
		uint8_t XTAL_REF_DIV;
		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
		#endif
		uint8_t DC_I2C_REG_RW_CNTL_STATUS;
		};

		@@ -217,9 +220,18 @@ struct dce_i2c_mask {
		uint32_t DC_I2C_INDEX;
		uint32_t DC_I2C_INDEX_WRITE;
		uint32_t XTAL_REF_DIV;
		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
		#endif
		uint32_t DC_I2C_REG_RW_CNTL_STATUS;
		};

		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
		I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
		I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
		#endif

		struct dce_i2c_registers {
		uint32_t SETUP;
		uint32_t SPEED;
		@@ -300,6 +312,16 @@ void dcn1_i2c_hw_construct(
		const struct dce_i2c_shift *shifts,
		const struct dce_i2c_mask *masks);

		#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
		void dcn2_i2c_hw_construct(
		struct dce_i2c_hw *dce_i2c_hw,
		struct dc_context *ctx,
		uint32_t engine_id,
		const struct dce_i2c_registers *regs,
		const struct dce_i2c_shift *shifts,
		const struct dce_i2c_mask *masks);
		#endif

		bool dce_i2c_submit_command_hw(
		struct resource_pool *pool,
		struct ddc *ddc,

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