Commit 38d32a75 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2 



Add emit_reg_wait implementation for UVD v7.

v2: call new function directly from the existing code

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ad68ee4

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+24 −16
Original line number Diff line number Diff line
@@ -1241,17 +1241,17 @@ static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 
	amdgpu_ring_write(ring, 8);

}



static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,

				uint32_t data0, uint32_t data1, uint32_t mask)

static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

					uint32_t val, uint32_t mask)

{

	struct amdgpu_device *adev = ring->adev;



	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

	amdgpu_ring_write(ring, data0);

	amdgpu_ring_write(ring, reg << 2);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

	amdgpu_ring_write(ring, data1);

	amdgpu_ring_write(ring, val);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));

	amdgpu_ring_write(ring, mask);
@@ -1271,16 +1271,16 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 
	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);



	/* wait for reg writes */

	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;

	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;

	data1 = lower_32_bits(pd_addr);

	mask = 0xffffffff;

	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);

	uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);



	/* wait for flush */

	data0 = (hub->vm_inv_eng0_ack + eng) << 2;

	data0 = hub->vm_inv_eng0_ack + eng;

	data1 = 1 << vmid;

	mask =  1 << vmid;

	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);

	uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);

}



static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -1298,6 +1298,16 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, HEVC_ENC_CMD_END);

}



static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,

					    uint32_t reg, uint32_t val,

					    uint32_t mask)

{

	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);

	amdgpu_ring_write(ring,	reg << 2);

	amdgpu_ring_write(ring, mask);

	amdgpu_ring_write(ring, val);

}



static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,

					    unsigned int vmid, unsigned pasid,

					    uint64_t pd_addr)
@@ -1308,16 +1318,12 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 
	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);



	/* wait for reg writes */

	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);

	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);

	amdgpu_ring_write(ring, 0xffffffff);

	amdgpu_ring_write(ring, lower_32_bits(pd_addr));

	uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,

					lower_32_bits(pd_addr), 0xffffffff);



	/* wait for flush */

	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);

	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);

	amdgpu_ring_write(ring, 1 << vmid);

	amdgpu_ring_write(ring, 1 << vmid);

	uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,

					1 << vmid, 1 << vmid);

}



static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
@@ -1676,6 +1682,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 
	.begin_use = amdgpu_uvd_ring_begin_use,

	.end_use = amdgpu_uvd_ring_end_use,

	.emit_wreg = uvd_v7_0_ring_emit_wreg,

	.emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,

};



static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
@@ -1704,6 +1711,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 
	.begin_use = amdgpu_uvd_ring_begin_use,

	.end_use = amdgpu_uvd_ring_end_use,

	.emit_wreg = uvd_v7_0_enc_ring_emit_wreg,

	.emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,

};



static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)

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