Commit 38a4f43d authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-arm-for-v4.12-rc5-take2' of... 

Merge tag 'kvm-arm-for-v4.12-rc5-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/ARM Fixes for v4.12-rc5 - Take 2

Changes include:
 - Fix an issue with migrating GICv2 VMs on GICv3 systems.
 - Squashed a bug for gicv3 when figuring out preemption levels.
 - Fix a potential null pointer derefence in KVM happening under memory
   pressure.
 - Maintain RES1 bits in the SCTLR_EL2 to make sure KVM works on new
   architecture revisions.
 - Allow unaligned accesses at EL2/HYP
parents d4912215 33b5c388

arch/arm/kvm/init.S

+2 −3
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ __do_hyp_init: 
	@  - Write permission implies XN: disabled

	@  - Instruction cache: enabled

	@  - Data/Unified cache: enabled

	@  - Memory alignment checks: enabled

	@  - MMU: enabled (this code must be run from an identity mapping)

	mrc	p15, 4, r0, c1, c0, 0	@ HSCR

	ldr	r2, =HSCTLR_MASK
@@ -112,8 +111,8 @@ __do_hyp_init: 
	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR

	ldr	r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)

	and	r1, r1, r2

 ARM(	ldr	r2, =(HSCTLR_M | HSCTLR_A)			)

 THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)		)

 ARM(	ldr	r2, =(HSCTLR_M)					)

 THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_TE)			)

	orr	r1, r1, r2

	orr	r0, r0, r1

	mcr	p15, 4, r0, c1, c0, 0	@ HSCR

arch/arm64/include/asm/sysreg.h

+4 −0
Original line number Diff line number Diff line
@@ -286,6 +286,10 @@ 
#define SCTLR_ELx_A	(1 << 1)

#define SCTLR_ELx_M	1



#define SCTLR_EL2_RES1	((1 << 4)  | (1 << 5)  | (1 << 11) | (1 << 16) | \

			 (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23) | \

			 (1 << 28) | (1 << 29))



#define SCTLR_ELx_FLAGS	(SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \

			 SCTLR_ELx_SA | SCTLR_ELx_I)

arch/arm64/kvm/hyp-init.S

+7 −4
Original line number Diff line number Diff line
@@ -106,10 +106,13 @@ __do_hyp_init: 
	tlbi	alle2

	dsb	sy



	mrs	x4, sctlr_el2

	and	x4, x4, #SCTLR_ELx_EE	// preserve endianness of EL2

	ldr	x5, =SCTLR_ELx_FLAGS

	orr	x4, x4, x5

	/*

	 * Preserve all the RES1 bits while setting the default flags,

	 * as well as the EE bit on BE. Drop the A flag since the compiler

	 * is allowed to generate unaligned accesses.

	 */

	ldr	x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))

CPU_BE(	orr	x4, x4, #SCTLR_ELx_EE)

	msr	sctlr_el2, x4

	isb

arch/arm64/kvm/vgic-sys-reg-v3.c

+5 −5
Original line number Diff line number Diff line
@@ -65,8 +65,8 @@ static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
		 * Here set VMCR.CTLR in ICC_CTLR_EL1 layout.

		 * The vgic_set_vmcr() will convert to ICH_VMCR layout.

		 */

		vmcr.ctlr = val & ICC_CTLR_EL1_CBPR_MASK;

		vmcr.ctlr |= val & ICC_CTLR_EL1_EOImode_MASK;

		vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;

		vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;

		vgic_set_vmcr(vcpu, &vmcr);

	} else {

		val = 0;
@@ -83,8 +83,8 @@ static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
		 * The VMCR.CTLR value is in ICC_CTLR_EL1 layout.

		 * Extract it directly using ICC_CTLR_EL1 reg definitions.

		 */

		val |= vmcr.ctlr & ICC_CTLR_EL1_CBPR_MASK;

		val |= vmcr.ctlr & ICC_CTLR_EL1_EOImode_MASK;

		val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;

		val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;



		p->regval = val;

	}
@@ -135,7 +135,7 @@ static bool access_gic_bpr1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
		p->regval = 0;



	vgic_get_vmcr(vcpu, &vmcr);

	if (!((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT)) {

	if (!vmcr.cbpr) {

		if (p->is_write) {

			vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>

				     ICC_BPR1_EL1_SHIFT;

include/linux/irqchip/arm-gic-v3.h

+4 −0
Original line number Diff line number Diff line
@@ -417,6 +417,10 @@ 
#define ICH_HCR_EN			(1 << 0)

#define ICH_HCR_UIE			(1 << 1)



#define ICH_VMCR_ACK_CTL_SHIFT		2

#define ICH_VMCR_ACK_CTL_MASK		(1 << ICH_VMCR_ACK_CTL_SHIFT)

#define ICH_VMCR_FIQ_EN_SHIFT		3

#define ICH_VMCR_FIQ_EN_MASK		(1 << ICH_VMCR_FIQ_EN_SHIFT)

#define ICH_VMCR_CBPR_SHIFT		4

#define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)

#define ICH_VMCR_EOIM_SHIFT		9

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