Commit 3846e6a0 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'sh-pfc-for-v5.2-tag1' of... 

Merge tag 'sh-pfc-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.2

  - Add HSCIF (serial) pin groups on R-Car H1,
  - Add I2C[035] pin groups on R-Car M3-N,
  - Add CANFD pin groups on RZ/G2M and RZ/G2E,
  - Retain SDHI/MMC clock return path delay configuration across
    suspend/resume on R-Car Gen3,
  - More validation of pinmux tables at build and runtime, including
    compile-test coverage of all drivers,
  - Small fixes, improvements, and cleanups.
parents d1ff8d07 0a042b35

arch/sh/include/cpu-sh4/cpu/sh7786.h

+1 −1
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ enum { 


static inline u32 sh7786_mm_sel(void)

{

	return __raw_readl(0xFC400020) & 0x7;

	return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7;

}



#endif /* __CPU_SH7786_H__ */

drivers/pinctrl/pinctrl-rza1.c

+2 −16
Original line number Diff line number Diff line
@@ -620,14 +620,7 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) 
static inline int rza1_pin_get_direction(struct rza1_port *port,

					 unsigned int pin)

{

	unsigned long irqflags;

	int input;



	spin_lock_irqsave(&port->lock, irqflags);

	input = rza1_get_bit(port, RZA1_PM_REG, pin);

	spin_unlock_irqrestore(&port->lock, irqflags);



	return !!input;

	return !!rza1_get_bit(port, RZA1_PM_REG, pin);

}



/**
@@ -671,14 +664,7 @@ static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, 


static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)

{

	unsigned long irqflags;

	int val;



	spin_lock_irqsave(&port->lock, irqflags);

	val = rza1_get_bit(port, RZA1_PPR_REG, pin);

	spin_unlock_irqrestore(&port->lock, irqflags);



	return val;

	return rza1_get_bit(port, RZA1_PPR_REG, pin);

}



/**

drivers/pinctrl/sh-pfc/Kconfig

+93 −111
Original line number Diff line number Diff line
@@ -3,201 +3,183 @@ 
# Renesas SH and SH Mobile PINCTRL drivers

#



if ARCH_RENESAS || SUPERH



config PINCTRL_SH_PFC

	bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)

	default y if ARCH_RENESAS || SUPERH

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	def_bool y

	select PINCTRL_PFC_EMEV2 if ARCH_EMEV2

	select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4

	select PINCTRL_PFC_R8A7740 if ARCH_R8A7740

	select PINCTRL_PFC_R8A7743 if ARCH_R8A7743

	select PINCTRL_PFC_R8A7744 if ARCH_R8A7744

	select PINCTRL_PFC_R8A7745 if ARCH_R8A7745

	select PINCTRL_PFC_R8A77470 if ARCH_R8A77470

	select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1

	select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0

	select PINCTRL_PFC_R8A7778 if ARCH_R8A7778

	select PINCTRL_PFC_R8A7779 if ARCH_R8A7779

	select PINCTRL_PFC_R8A7790 if ARCH_R8A7790

	select PINCTRL_PFC_R8A7791 if ARCH_R8A7791

	select PINCTRL_PFC_R8A7792 if ARCH_R8A7792

	select PINCTRL_PFC_R8A7793 if ARCH_R8A7793

	select PINCTRL_PFC_R8A7794 if ARCH_R8A7794

	select PINCTRL_PFC_R8A7795 if ARCH_R8A7795

	select PINCTRL_PFC_R8A7796 if ARCH_R8A7796

	select PINCTRL_PFC_R8A77965 if ARCH_R8A77965

	select PINCTRL_PFC_R8A77970 if ARCH_R8A77970

	select PINCTRL_PFC_R8A77980 if ARCH_R8A77980

	select PINCTRL_PFC_R8A77990 if ARCH_R8A77990

	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269

	select PINCTRL_PFC_SH73A0 if ARCH_SH73A0

	select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720

	select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722

	select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723

	select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724

	select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734

	select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757

	select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785

	select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786

	select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3

	help

	  This enables pin control drivers for SH and SH Mobile platforms

	  This enables pin control drivers for Renesas SuperH and ARM platforms



config PINCTRL_SH_PFC_GPIO

	select GPIOLIB

	select PINCTRL_SH_PFC

	bool

	help

	  This enables pin control and GPIO drivers for SH/SH Mobile platforms



config PINCTRL_SH_FUNC_GPIO

	select PINCTRL_SH_PFC_GPIO

	bool

	help

	  This enables legacy function GPIOs for SH platforms



config PINCTRL_PFC_EMEV2

	def_bool y

	depends on ARCH_EMEV2

	select PINCTRL_SH_PFC

	bool "Emma Mobile AV2 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A73A4

	def_bool y

	depends on ARCH_R8A73A4

	bool "R-Mobile APE6 pin control support" if COMPILE_TEST

	select PINCTRL_SH_PFC_GPIO



config PINCTRL_PFC_R8A7740

	def_bool y

	depends on ARCH_R8A7740

	bool "R-Mobile A1 pin control support" if COMPILE_TEST

	select PINCTRL_SH_PFC_GPIO



config PINCTRL_PFC_R8A7743

	def_bool y

	depends on ARCH_R8A7743

	select PINCTRL_SH_PFC

	bool "RZ/G1M pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7744

	def_bool y

	depends on ARCH_R8A7744

	select PINCTRL_SH_PFC

	bool "RZ/G1N pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7745

        def_bool y

        depends on ARCH_R8A7745

        select PINCTRL_SH_PFC

	bool "RZ/G1E pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77470

        def_bool y

        depends on ARCH_R8A77470

        select PINCTRL_SH_PFC

	bool "RZ/G1C pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A774A1

        def_bool y

        depends on ARCH_R8A774A1

        select PINCTRL_SH_PFC

	bool "RZ/G2M pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A774C0

        def_bool y

        depends on ARCH_R8A774C0

        select PINCTRL_SH_PFC

	bool "RZ/G2E pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7778

	def_bool y

	depends on ARCH_R8A7778

	select PINCTRL_SH_PFC

	bool "R-Car M1A pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7779

	def_bool y

	depends on ARCH_R8A7779

	select PINCTRL_SH_PFC

	bool "R-Car H1 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7790

	def_bool y

	depends on ARCH_R8A7790

	select PINCTRL_SH_PFC

	bool "R-Car H2 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7791

	def_bool y

	depends on ARCH_R8A7791

	select PINCTRL_SH_PFC

	bool "R-Car M2-W pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7792

	def_bool y

	depends on ARCH_R8A7792

	select PINCTRL_SH_PFC

	bool "R-Car V2H pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7793

	def_bool y

	depends on ARCH_R8A7793

	select PINCTRL_SH_PFC

	bool "R-Car M2-N pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7794

	def_bool y

	depends on ARCH_R8A7794

	select PINCTRL_SH_PFC

	bool "R-Car E2 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7795

	def_bool y

	depends on ARCH_R8A7795

	select PINCTRL_SH_PFC

	bool "R-Car H3 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A7796

        def_bool y

        depends on ARCH_R8A7796

        select PINCTRL_SH_PFC

	bool "R-Car M3-W pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77965

        def_bool y

        depends on ARCH_R8A77965

        select PINCTRL_SH_PFC

	bool "R-Car M3-N pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77970

	def_bool y

	depends on ARCH_R8A77970

	select PINCTRL_SH_PFC

	bool "R-Car V3M pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77980

	def_bool y

	depends on ARCH_R8A77980

	select PINCTRL_SH_PFC

	bool "R-Car V3H pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77990

        def_bool y

        depends on ARCH_R8A77990

        select PINCTRL_SH_PFC

	bool "R-Car E3 pin control support" if COMPILE_TEST



config PINCTRL_PFC_R8A77995

        def_bool y

        depends on ARCH_R8A77995

        select PINCTRL_SH_PFC

	bool "R-Car D3 pin control support" if COMPILE_TEST



config PINCTRL_PFC_SH7203

	def_bool y

	depends on CPU_SUBTYPE_SH7203

	select PINCTRL_SH_PFC_GPIO

	bool "SH7203 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7264

	def_bool y

	depends on CPU_SUBTYPE_SH7264

	select PINCTRL_SH_PFC_GPIO

	bool "SH7264 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7269

	def_bool y

	depends on CPU_SUBTYPE_SH7269

	select PINCTRL_SH_PFC_GPIO

	bool "SH7269 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH73A0

	def_bool y

	depends on ARCH_SH73A0

	bool "SH-Mobile AG5 pin control support" if COMPILE_TEST

	select PINCTRL_SH_PFC_GPIO

	select REGULATOR



config PINCTRL_PFC_SH7720

	def_bool y

	depends on CPU_SUBTYPE_SH7720

	select PINCTRL_SH_PFC_GPIO

	bool "SH7720 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7722

	def_bool y

	depends on CPU_SUBTYPE_SH7722

	select PINCTRL_SH_PFC_GPIO

	bool "SH7722 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7723

	def_bool y

	depends on CPU_SUBTYPE_SH7723

	select PINCTRL_SH_PFC_GPIO

	bool "SH-Mobile R2 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7724

	def_bool y

	depends on CPU_SUBTYPE_SH7724

	select PINCTRL_SH_PFC_GPIO

	bool "SH-Mobile R2R pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7734

	def_bool y

	depends on CPU_SUBTYPE_SH7734

	select PINCTRL_SH_PFC_GPIO

	bool "SH7734 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7757

	def_bool y

	depends on CPU_SUBTYPE_SH7757

	select PINCTRL_SH_PFC_GPIO

	bool "SH7757 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7785

	def_bool y

	depends on CPU_SUBTYPE_SH7785

	select PINCTRL_SH_PFC_GPIO

	bool "SH7785 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SH7786

	def_bool y

	depends on CPU_SUBTYPE_SH7786

	select PINCTRL_SH_PFC_GPIO

	bool "SH7786 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO



config PINCTRL_PFC_SHX3

	def_bool y

	depends on CPU_SUBTYPE_SHX3

	select PINCTRL_SH_PFC_GPIO

endif
 
	bool "SH-X3 pin control support" if COMPILE_TEST

	select PINCTRL_SH_FUNC_GPIO

drivers/pinctrl/sh-pfc/Makefile

+15 −0
Original line number Diff line number Diff line
@@ -38,3 +38,18 @@ obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o 
obj-$(CONFIG_PINCTRL_PFC_SH7785)	+= pfc-sh7785.o

obj-$(CONFIG_PINCTRL_PFC_SH7786)	+= pfc-sh7786.o

obj-$(CONFIG_PINCTRL_PFC_SHX3)		+= pfc-shx3.o



ifeq ($(CONFIG_COMPILE_TEST),y)

CFLAGS_pfc-sh7203.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a

CFLAGS_pfc-sh7264.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a

CFLAGS_pfc-sh7269.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a

CFLAGS_pfc-sh7720.o	+= -I$(srctree)/arch/sh/include/cpu-sh3

CFLAGS_pfc-sh7722.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7723.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7724.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7734.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7757.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7785.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-sh7786.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

CFLAGS_pfc-shx3.o	+= -I$(srctree)/arch/sh/include/cpu-sh4

endif

drivers/pinctrl/sh-pfc/core.c

+130 −0
Original line number Diff line number Diff line
@@ -571,6 +571,13 @@ static const struct of_device_id sh_pfc_of_table[] = { 
		.compatible = "renesas,pfc-r8a7795",

		.data = &r8a7795_pinmux_info,

	},

#ifdef DEBUG

	{

		/* For sanity checks only (nothing matches against this) */

		.compatible = "renesas,pfc-r8a77950",	/* R-Car H3 ES1.0 */

		.data = &r8a7795es1_pinmux_info,

	},

#endif /* DEBUG */

#endif

#ifdef CONFIG_PINCTRL_PFC_R8A7796

	{
@@ -709,6 +716,128 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } 
#define DEV_PM_OPS	NULL

#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */



#ifdef DEBUG

static bool is0s(const u16 *enum_ids, unsigned int n)

{

	unsigned int i;



	for (i = 0; i < n; i++)

		if (enum_ids[i])

			return false;



	return true;

}



static unsigned int sh_pfc_errors;

static unsigned int sh_pfc_warnings;



static void sh_pfc_check_cfg_reg(const char *drvname,

				 const struct pinmux_cfg_reg *cfg_reg)

{

	unsigned int i, n, rw, fw;



	if (cfg_reg->field_width) {

		/* Checked at build time */

		return;

	}



	for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {

		if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {

			pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",

				drvname, cfg_reg->reg, rw, rw + fw - 1);

			sh_pfc_warnings++;

		}

		n += 1 << fw;

		rw += fw;

	}



	if (rw != cfg_reg->reg_width) {

		pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",

		       drvname, cfg_reg->reg, rw, cfg_reg->reg_width);

		sh_pfc_errors++;

	}



	if (n != cfg_reg->nr_enum_ids) {

		pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",

		       drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);

		sh_pfc_errors++;

	}

}



static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)

{

	const struct sh_pfc_function *func;

	const char *drvname = info->name;

	unsigned int *refcnts;

	unsigned int i, j, k;



	pr_info("Checking %s\n", drvname);



	/* Check groups and functions */

	refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);

	if (!refcnts)

		return;



	for (i = 0; i < info->nr_functions; i++) {

		func = &info->functions[i];

		for (j = 0; j < func->nr_groups; j++) {

			for (k = 0; k < info->nr_groups; k++) {

				if (!strcmp(func->groups[j],

					    info->groups[k].name)) {

					refcnts[k]++;

					break;

				}

			}



			if (k == info->nr_groups) {

				pr_err("%s: function %s: group %s not found\n",

				       drvname, func->name, func->groups[j]);

				sh_pfc_errors++;

			}

		}

	}



	for (i = 0; i < info->nr_groups; i++) {

		if (!refcnts[i]) {

			pr_err("%s: orphan group %s\n", drvname,

			       info->groups[i].name);

			sh_pfc_errors++;

		} else if (refcnts[i] > 1) {

			pr_err("%s: group %s referred by %u functions\n",

			       drvname, info->groups[i].name, refcnts[i]);

			sh_pfc_warnings++;

		}

	}



	kfree(refcnts);



	/* Check config register descriptions */

	for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)

		sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);

}



static void sh_pfc_check_driver(const struct platform_driver *pdrv)

{

	unsigned int i;



	pr_warn("Checking builtin pinmux tables\n");



	for (i = 0; pdrv->id_table[i].name[0]; i++)

		sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);



#ifdef CONFIG_OF

	for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)

		sh_pfc_check_info(pdrv->driver.of_match_table[i].data);

#endif



	pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,

		sh_pfc_warnings);

}



#else /* !DEBUG */

static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}

#endif /* !DEBUG */



static int sh_pfc_probe(struct platform_device *pdev)

{

#ifdef CONFIG_OF
@@ -840,6 +969,7 @@ static struct platform_driver sh_pfc_driver = { 


static int __init sh_pfc_init(void)

{

	sh_pfc_check_driver(&sh_pfc_driver);

	return platform_driver_register(&sh_pfc_driver);

}

postcore_initcall(sh_pfc_init);

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