Commit 383ffda2 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: EXYNOS: no more support non-DT for EXYNOS SoCs 



As we discussed in mailing list, non-DT for EXYNOS SoCs will not be
supported from v3.11. This patch removes regarding files for non-DT
including board files and defconfig.

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 317ddd25

arch/arm/mach-exynos/Kconfig

+1 −319
Original line number Diff line number Diff line
@@ -84,329 +84,11 @@ config SOC_EXYNOS5440 
	help

	  Enable EXYNOS5440 SoC support



config EXYNOS_ATAGS

	bool "ATAGS based boot for EXYNOS (deprecated)"

	depends on !ARCH_MULTIPLATFORM

	depends on ATAGS

	default y

	help

	  The EXYNOS platform is moving towards being completely probed

	  through device tree. This enables support for board files using

	  the traditional ATAGS boot format.

	  Note that this option is not available for multiplatform builds.



if EXYNOS_ATAGS



config EXYNOS_DEV_DMA

	bool

	help

	  Compile in amba device definitions for DMA controller



config EXYNOS4_DEV_AHCI

	bool

	help

	  Compile in platform device definitions for AHCI



config EXYNOS4_SETUP_FIMD0

	bool

	help

	  Common setup code for FIMD0.



config EXYNOS4_DEV_USB_OHCI

	bool

	help

	  Compile in platform device definition for USB OHCI



config EXYNOS4_SETUP_I2C1

	bool

	help

	  Common setup code for i2c bus 1.



config EXYNOS4_SETUP_I2C2

	bool

	help

	  Common setup code for i2c bus 2.



config EXYNOS4_SETUP_I2C3

	bool

	help

	  Common setup code for i2c bus 3.



config EXYNOS4_SETUP_I2C4

	bool

	help

	  Common setup code for i2c bus 4.



config EXYNOS4_SETUP_I2C5

	bool

	help

	  Common setup code for i2c bus 5.



config EXYNOS4_SETUP_I2C6

	bool

	help

	  Common setup code for i2c bus 6.



config EXYNOS4_SETUP_I2C7

	bool

	help

	  Common setup code for i2c bus 7.



config EXYNOS4_SETUP_KEYPAD

	bool

	help

	  Common setup code for keypad.



config EXYNOS4_SETUP_SDHCI

	bool

	select EXYNOS4_SETUP_SDHCI_GPIO

	help

	  Internal helper functions for EXYNOS4 based SDHCI systems.



config EXYNOS4_SETUP_SDHCI_GPIO

	bool

	help

	  Common setup code for SDHCI gpio.



config EXYNOS4_SETUP_FIMC

	bool

	help

	  Common setup code for the camera interfaces.



config EXYNOS4_SETUP_USB_PHY

	bool

	help

	  Common setup code for USB PHY controller



config EXYNOS_SETUP_SPI

	bool

	help

	  Common setup code for SPI GPIO configurations.



# machine support



if ARCH_EXYNOS4



comment "EXYNOS4210 Boards"



config MACH_SMDKC210

	bool "SMDKC210"

	select MACH_SMDKV310

	help

	  Machine support for Samsung SMDKC210



config MACH_SMDKV310

	bool "SMDKV310"

	select CPU_EXYNOS4210

	select EXYNOS4_DEV_AHCI

	select EXYNOS4_DEV_USB_OHCI

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_KEYPAD

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	select EXYNOS_DEV_DMA

	select EXYNOS_DEV_SYSMMU

	select S3C24XX_PWM

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC1

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_RTC

	select S3C_DEV_USB_HSOTG

	select S3C_DEV_WDT

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_G2D

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_JPEG

	select S5P_DEV_MFC

	select S5P_DEV_TV

	select S5P_DEV_USB_EHCI

	select SAMSUNG_DEV_BACKLIGHT

	select SAMSUNG_DEV_KEYPAD

	select SAMSUNG_DEV_PWM

	help

	  Machine support for Samsung SMDKV310



config MACH_ARMLEX4210

	bool "ARMLEX4210"

	select CPU_EXYNOS4210

	select EXYNOS4_DEV_AHCI

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS_DEV_DMA

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_RTC

	select S3C_DEV_WDT

	help

	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210



config MACH_UNIVERSAL_C210

	bool "Mobile UNIVERSAL_C210 Board"

	select CLKSRC_MMIO

	select CLKSRC_SAMSUNG_PWM

	select CPU_EXYNOS4210

	select EXYNOS4_SETUP_FIMC

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C5

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	select EXYNOS_DEV_DMA

	select EXYNOS_DEV_SYSMMU

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_I2C3

	select S3C_DEV_I2C5

	select S3C_DEV_USB_HSOTG

	select S5P_DEV_CSIS0

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_G2D

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_JPEG

	select S5P_DEV_MFC

	select S5P_DEV_ONENAND

	select S5P_DEV_TV

	select S5P_GPIO_INT

	select S5P_SETUP_MIPIPHY

	help

	  Machine support for Samsung Mobile Universal S5PC210 Reference

	  Board.



config MACH_NURI

	bool "Mobile NURI Board"

	select CPU_EXYNOS4210

	select EXYNOS4_SETUP_FIMC

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C5

	select EXYNOS4_SETUP_I2C6

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	select EXYNOS_DEV_DMA

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_I2C3

	select S3C_DEV_I2C5

	select S3C_DEV_I2C6

	select S3C_DEV_RTC

	select S3C_DEV_USB_HSOTG

	select S3C_DEV_WDT

	select S5P_DEV_CSIS0

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_G2D

	select S5P_DEV_JPEG

	select S5P_DEV_MFC

	select S5P_DEV_USB_EHCI

	select S5P_GPIO_INT

	select S5P_SETUP_MIPIPHY

	select SAMSUNG_DEV_ADC

	select SAMSUNG_DEV_PWM

	help

	  Machine support for Samsung Mobile NURI Board.



config MACH_ORIGEN

	bool "ORIGEN"

	select CPU_EXYNOS4210

	select EXYNOS4_DEV_USB_OHCI

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	select EXYNOS_DEV_DMA

	select EXYNOS_DEV_SYSMMU

	select S3C24XX_PWM

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC2

	select S3C_DEV_RTC

	select S3C_DEV_USB_HSOTG

	select S3C_DEV_WDT

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_G2D

	select S5P_DEV_I2C_HDMIPHY

	select S5P_DEV_JPEG

	select S5P_DEV_MFC

	select S5P_DEV_TV

	select S5P_DEV_USB_EHCI

	select SAMSUNG_DEV_BACKLIGHT

	select SAMSUNG_DEV_PWM

	help

	  Machine support for ORIGEN based on Samsung EXYNOS4210



comment "EXYNOS4212 Boards"



config MACH_SMDK4212

	bool "SMDK4212"

	select EXYNOS4_SETUP_FIMD0

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C7

	select EXYNOS4_SETUP_KEYPAD

	select EXYNOS4_SETUP_SDHCI

	select EXYNOS4_SETUP_USB_PHY

	select EXYNOS_DEV_DMA

	select EXYNOS_DEV_SYSMMU

	select S3C24XX_PWM

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_I2C3

	select S3C_DEV_I2C7

	select S3C_DEV_RTC

	select S3C_DEV_USB_HSOTG

	select S3C_DEV_WDT

	select S5P_DEV_FIMC0

	select S5P_DEV_FIMC1

	select S5P_DEV_FIMC2

	select S5P_DEV_FIMC3

	select S5P_DEV_FIMD0

	select S5P_DEV_MFC

	select SAMSUNG_DEV_BACKLIGHT

	select SAMSUNG_DEV_KEYPAD

	select SAMSUNG_DEV_PWM

	select SOC_EXYNOS4212

	help

	  Machine support for Samsung SMDK4212



comment "EXYNOS4412 Boards"



config MACH_SMDK4412

	bool "SMDK4412"

	select MACH_SMDK4212

	select SOC_EXYNOS4412

	help

	  Machine support for Samsung SMDK4412

endif



endif



comment "Flattened Device Tree based board for EXYNOS SoCs"



config MACH_EXYNOS4_DT

	bool "Samsung Exynos4 Machine using device tree"

	default y

	depends on ARCH_EXYNOS4

	select ARM_AMBA

	select CLKSRC_OF

arch/arm/mach-exynos/Makefile

+0 −26
Original line number Diff line number Diff line
@@ -32,16 +32,6 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) 


# machine support



obj-$(CONFIG_MACH_SMDKC210)		+= mach-smdkv310.o

obj-$(CONFIG_MACH_SMDKV310)		+= mach-smdkv310.o

obj-$(CONFIG_MACH_ARMLEX4210)		+= mach-armlex4210.o

obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o

obj-$(CONFIG_MACH_NURI)			+= mach-nuri.o

obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o



obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o

obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o



obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o

obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
@@ -49,21 +39,5 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o 


obj-y					+= dev-uart.o

obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o

obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o

obj-$(CONFIG_EXYNOS_DEV_DMA)		+= dma.o

obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o



obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
 
obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o

obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)	+= setup-fimd0.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C1)	+= setup-i2c1.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C2)	+= setup-i2c2.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C3)	+= setup-i2c3.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C4)	+= setup-i2c4.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C5)	+= setup-i2c5.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C6)	+= setup-i2c6.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o

obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o

obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o

obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)	+= setup-usb-phy.o

obj-$(CONFIG_EXYNOS_SETUP_SPI)		+= setup-spi.o

arch/arm/mach-exynos/common.c

+0 −10
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ void __init exynos_init_late(void) 
	exynos_pm_late_initcall();

}



#ifdef CONFIG_OF

int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,

					int depth, void *data)

{
@@ -376,7 +375,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, 
	iotable_init(&iodesc, 1);

	return 1;

}

#endif



/*

 * exynos_map_io
@@ -388,11 +386,9 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size) 
{

	debug_ll_io_init();



#ifdef CONFIG_OF

	if (initial_boot_params)

		of_scan_flat_dt(exynos_fdt_map_chipid, NULL);

	else

#endif

		iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));



	if (mach_desc)
@@ -475,10 +471,8 @@ void __init exynos_init_time(void) 
	};



	if (of_have_populated_dt()) {

#ifdef CONFIG_OF

		of_clk_init(NULL);

		clocksource_of_init();

#endif

	} else {

		/* todo: remove after migrating legacy E4 platforms to dt */

#ifdef CONFIG_ARCH_EXYNOS4
@@ -517,10 +511,8 @@ void __init exynos4_init_irq(void) 


	if (!of_have_populated_dt())

		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);

#ifdef CONFIG_OF

	else

		irqchip_init();

#endif



	if (!of_have_populated_dt())

		combiner_init(S5P_VA_COMBINER_BASE, NULL,
@@ -531,9 +523,7 @@ void __init exynos4_init_irq(void) 


void __init exynos5_init_irq(void)

{

#ifdef CONFIG_OF

	irqchip_init();

#endif

	gic_arch_extn.irq_set_wake = s3c_irq_wake;

}

arch/arm/mach-exynos/dev-ahci.c

deleted100644 → 0
+0 −255
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-exynos4/dev-ahci.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4 - AHCI support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/dma-mapping.h>

#include <linux/platform_device.h>

#include <linux/ahci_platform.h>



#include <plat/cpu.h>



#include <mach/irqs.h>

#include <mach/map.h>

#include <mach/regs-pmu.h>



/* PHY Control Register */

#define SATA_CTRL0		0x0

/* PHY Link Control Register */

#define SATA_CTRL1		0x4

/* PHY Status Register */

#define SATA_PHY_STATUS		0x8



#define SATA_CTRL0_RX_DATA_VALID(x)	(x << 27)

#define SATA_CTRL0_SPEED_MODE		(1 << 26)

#define SATA_CTRL0_M_PHY_CAL		(1 << 19)

#define SATA_CTRL0_PHY_CMU_RST_N	(1 << 10)

#define SATA_CTRL0_M_PHY_LN_RST_N	(1 << 9)

#define SATA_CTRL0_PHY_POR_N		(1 << 8)



#define SATA_CTRL1_RST_PMALIVE_N	(1 << 8)

#define SATA_CTRL1_RST_RXOOB_N		(1 << 7)

#define SATA_CTRL1_RST_RX_N		(1 << 6)

#define SATA_CTRL1_RST_TX_N		(1 << 5)



#define SATA_PHY_STATUS_CMU_OK		(1 << 18)

#define SATA_PHY_STATUS_LANE_OK		(1 << 16)



#define LANE0		0x200

#define COM_LANE	0xA00



#define HOST_PORTS_IMPL	0xC

#define SCLK_SATA_FREQ	(67 * MHZ)



static void __iomem *phy_base, *phy_ctrl;



struct phy_reg {

	u8	reg;

	u8	val;

};



/* SATA PHY setup */

static const struct phy_reg exynos4_sataphy_cmu[] = {

	{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },

	{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },

	{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },

	{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },

	{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },

	{ 0x6b, 0xc8 }, { 0x6c, 0x06 },

};



static const struct phy_reg exynos4_sataphy_lane[] = {

	{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },

	{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },

	{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },

	{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },

	{ 0x51, 0x0f },

};



static const struct phy_reg exynos4_sataphy_comlane[] = {

	{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },

	{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },

	{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },

	{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },

	{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },

	{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },

	{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },

	{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },

	{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },

	{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },

	{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },

	{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },

	{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },

	{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },

};



static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)

{

	unsigned long timeout;



	/* wait for maximum of 3 sec */

	timeout = jiffies + msecs_to_jiffies(3000);

	while (!(__raw_readl(reg) & bit)) {

		if (time_after(jiffies, timeout))

			return -1;

		cpu_relax();

	}

	return 0;

}



static int ahci_phy_init(void __iomem *mmio)

{

	int i, ctrl0;



	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)

		__raw_writeb(exynos4_sataphy_cmu[i].val,

		phy_base + (exynos4_sataphy_cmu[i].reg * 4));



	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)

		__raw_writeb(exynos4_sataphy_lane[i].val,

		phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);



	for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)

		__raw_writeb(exynos4_sataphy_comlane[i].val,

		phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);



	__raw_writeb(0x07, phy_base);



	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);

	ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;

	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);



	if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,

				SATA_PHY_STATUS_CMU_OK) < 0) {

		printk(KERN_ERR "PHY CMU not ready\n");

		return -EBUSY;

	}



	__raw_writeb(0x03, phy_base + (COM_LANE * 4));



	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);

	ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;

	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);



	if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,

				SATA_PHY_STATUS_LANE_OK) < 0) {

		printk(KERN_ERR "PHY LANE not ready\n");

		return -EBUSY;

	}



	ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);

	ctrl0 |= SATA_CTRL0_M_PHY_CAL;

	__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);



	return 0;

}



static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)

{

	struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;

	int val, ret;



	phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);

	if (!phy_base) {

		dev_err(dev, "failed to allocate memory for SATA PHY\n");

		return -ENOMEM;

	}



	phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);

	if (!phy_ctrl) {

		dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");

		ret = -ENOMEM;

		goto err1;

	}



	clk_sata = clk_get(dev, "sata");

	if (IS_ERR(clk_sata)) {

		dev_err(dev, "failed to get sata clock\n");

		ret = PTR_ERR(clk_sata);

		clk_sata = NULL;

		goto err2;



	}

	clk_enable(clk_sata);



	clk_sataphy = clk_get(dev, "sataphy");

	if (IS_ERR(clk_sataphy)) {

		dev_err(dev, "failed to get sataphy clock\n");

		ret = PTR_ERR(clk_sataphy);

		clk_sataphy = NULL;

		goto err3;

	}

	clk_enable(clk_sataphy);



	clk_sclk_sata = clk_get(dev, "sclk_sata");

	if (IS_ERR(clk_sclk_sata)) {

		dev_err(dev, "failed to get sclk_sata\n");

		ret = PTR_ERR(clk_sclk_sata);

		clk_sclk_sata = NULL;

		goto err4;

	}

	clk_enable(clk_sclk_sata);

	clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);



	__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);



	/* Enable PHY link control */

	val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |

			SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;

	__raw_writel(val, phy_ctrl + SATA_CTRL1);



	/* Set communication speed as 3Gbps and enable PHY power */

	val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |

			SATA_CTRL0_PHY_POR_N;

	__raw_writel(val, phy_ctrl + SATA_CTRL0);



	/* Port0 is available */

	__raw_writel(0x1, mmio + HOST_PORTS_IMPL);



	return ahci_phy_init(mmio);



err4:

	clk_disable(clk_sataphy);

	clk_put(clk_sataphy);

err3:

	clk_disable(clk_sata);

	clk_put(clk_sata);

err2:

	iounmap(phy_ctrl);

err1:

	iounmap(phy_base);



	return ret;

}



static struct ahci_platform_data exynos4_ahci_pdata = {

	.init = exynos4_ahci_init,

};



static struct resource exynos4_ahci_resource[] = {

	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),

	[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),

};



static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);



struct platform_device exynos4_device_ahci = {

	.name		= "ahci",

	.id		= -1,

	.resource	= exynos4_ahci_resource,

	.num_resources	= ARRAY_SIZE(exynos4_ahci_resource),

	.dev		= {

		.platform_data		= &exynos4_ahci_pdata,

		.dma_mask		= &exynos4_ahci_dmamask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	},

};

arch/arm/mach-exynos/dev-ohci.c

deleted100644 → 0
+0 −52
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-exynos/dev-ohci.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS - OHCI support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/dma-mapping.h>

#include <linux/platform_device.h>

#include <linux/platform_data/usb-ohci-exynos.h>



#include <mach/irqs.h>

#include <mach/map.h>



#include <plat/devs.h>

#include <plat/usb-phy.h>



static struct resource exynos4_ohci_resource[] = {

	[0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),

	[1] = DEFINE_RES_IRQ(IRQ_USB_HOST),

};



static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);



struct platform_device exynos4_device_ohci = {

	.name		= "exynos-ohci",

	.id		= -1,

	.num_resources	= ARRAY_SIZE(exynos4_ohci_resource),

	.resource	= exynos4_ohci_resource,

	.dev		= {

		.dma_mask		= &exynos4_ohci_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	}

};



void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)

{

	struct exynos4_ohci_platdata *npd;



	npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),

			&exynos4_device_ohci);



	if (!npd->phy_init)

		npd->phy_init = s5p_usb_phy_init;

	if (!npd->phy_exit)

		npd->phy_exit = s5p_usb_phy_exit;

}

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