Commit 383b9961 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
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arm: mach-mv78xx0: use IOMEM() for base address definitions



We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-mv78xx0 code.

Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 060f3d19
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+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
	 * so we don't need to take that into account here.
	 */

	return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
	return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
}

/*
+14 −9
Original line number Diff line number Diff line
@@ -130,17 +130,17 @@ static int get_tclk(void)
 ****************************************************************************/
static struct map_desc mv78xx0_io_desc[] __initdata = {
	{
		.virtual	= MV78XX0_CORE_REGS_VIRT_BASE,
		.virtual	= (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
		.pfn		= 0,
		.length		= MV78XX0_CORE_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_PCIE_IO_VIRT_BASE(0),
		.virtual	= (unsigned long) MV78XX0_PCIE_IO_VIRT_BASE(0),
		.pfn		= __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
		.length		= MV78XX0_PCIE_IO_SIZE * 8,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_REGS_VIRT_BASE,
		.virtual	= (unsigned long) MV78XX0_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
		.length		= MV78XX0_REGS_SIZE,
		.type		= MT_DEVICE,
@@ -300,7 +300,8 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 ****************************************************************************/
void __init mv78xx0_uart0_init(void)
{
	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
			 UART0_PHYS_BASE,
			 IRQ_MV78XX0_UART_0, tclk);
}

@@ -310,7 +311,8 @@ void __init mv78xx0_uart0_init(void)
 ****************************************************************************/
void __init mv78xx0_uart1_init(void)
{
	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
			 UART1_PHYS_BASE,
			 IRQ_MV78XX0_UART_1, tclk);
}

@@ -320,7 +322,8 @@ void __init mv78xx0_uart1_init(void)
 ****************************************************************************/
void __init mv78xx0_uart2_init(void)
{
	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
	orion_uart2_init((unsigned long) UART2_VIRT_BASE,
			 UART2_PHYS_BASE,
			 IRQ_MV78XX0_UART_2, tclk);
}

@@ -329,7 +332,8 @@ void __init mv78xx0_uart2_init(void)
 ****************************************************************************/
void __init mv78xx0_uart3_init(void)
{
	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
	orion_uart3_init((unsigned long) UART3_VIRT_BASE,
			 UART3_PHYS_BASE,
			 IRQ_MV78XX0_UART_3, tclk);
}

@@ -338,12 +342,13 @@ void __init mv78xx0_uart3_init(void)
 ****************************************************************************/
void __init mv78xx0_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
}

static void mv78xx0_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
			BRIDGE_INT_TIMER1_CLR,
			IRQ_MV78XX0_TIMER_1, get_tclk());
}

+3 −3
Original line number Diff line number Diff line
@@ -41,16 +41,16 @@
 */
#define MV78XX0_CORE0_REGS_PHYS_BASE	0xf1020000
#define MV78XX0_CORE1_REGS_PHYS_BASE	0xf1024000
#define MV78XX0_CORE_REGS_VIRT_BASE	0xfe400000
#define MV78XX0_CORE_REGS_VIRT_BASE	IOMEM(0xfe400000)
#define MV78XX0_CORE_REGS_PHYS_BASE	0xfe400000
#define MV78XX0_CORE_REGS_SIZE		SZ_16K

#define MV78XX0_PCIE_IO_PHYS_BASE(i)	(0xf0800000 + ((i) << 20))
#define MV78XX0_PCIE_IO_VIRT_BASE(i)	(0xfe700000 + ((i) << 20))
#define MV78XX0_PCIE_IO_VIRT_BASE(i)	IOMEM(0xfe700000 + ((i) << 20))
#define MV78XX0_PCIE_IO_SIZE		SZ_1M

#define MV78XX0_REGS_PHYS_BASE		0xf1000000
#define MV78XX0_REGS_VIRT_BASE		0xfef00000
#define MV78XX0_REGS_VIRT_BASE		IOMEM(0xfef00000)
#define MV78XX0_REGS_SIZE		SZ_1M

#define MV78XX0_PCIE_MEM_PHYS_BASE	0xc0000000
+5 −4
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"
@@ -23,16 +24,16 @@ static int __initdata gpio0_irqs[4] = {

void __init mv78xx0_init_irq(void)
{
	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
	orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);

	/*
	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
	 * registers for core #1 are at an offset of 0x18 from those of
	 * core #0.)
	 */
	orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
	orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
			mv78xx0_core_index() ? 0x18 : 0,
			IRQ_MV78XX0_GPIO_START, gpio0_irqs);
}
+2 −1
Original line number Diff line number Diff line
@@ -33,5 +33,6 @@ static unsigned int __init mv78xx0_variant(void)
void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
{
	orion_mpp_conf(mpp_list, mv78xx0_variant(),
		       MPP_MAX, DEV_BUS_VIRT_BASE);
		       MPP_MAX,
		       (unsigned long) DEV_BUS_VIRT_BASE);
}
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