Commit 380f0423 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Move ringbuffer WAs to engine workaround list 



Now that intel_engine_apply_workarounds is called on all gens, we can
use the engine workaround lists for pre-gen8 workarounds as well to be
consistent in the way we handle and dump the WAs.

v2: Ignore the sanity check of MI_MODE on Broadwater, for whatever reason
it is not sticking.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200201194004.3622493-1-chris@chris-wilson.co.uk
parent eeec73f8

drivers/gpu/drm/i915/gt/intel_ring_submission.c

+0 −37
Original line number Diff line number Diff line
@@ -858,43 +858,6 @@ static int rcs_resume(struct intel_engine_cs *engine) 
		intel_uncore_write(uncore, ECOSKPD,

			   _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));



	/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */

	if (IS_GEN_RANGE(i915, 4, 6))

		intel_uncore_write(uncore, MI_MODE,

				   _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));



	/* We need to disable the AsyncFlip performance optimisations in order

	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be

	 * programmed to '1' on all products.

	 *

	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv

	 */

	if (IS_GEN_RANGE(i915, 6, 7))

		intel_uncore_write(uncore, MI_MODE,

				   _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));



	/* Required for the hardware to program scanline values for waiting */

	/* WaEnableFlushTlbInvalidationMode:snb */

	if (IS_GEN(i915, 6))

		intel_uncore_write(uncore, GFX_MODE,

			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));



	/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */

	if (IS_GEN(i915, 7))

		intel_uncore_write(uncore, GFX_MODE_GEN7,

			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |

			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));



	if (IS_GEN(i915, 6)) {

		/* From the Sandybridge PRM, volume 1 part 3, page 24:

		 * "If this bit is set, STCunit will have LRA as replacement

		 *  policy. [...] This bit must be reset.  LRA replacement

		 *  policy is not supported."

		 */

		intel_uncore_write(uncore, CACHE_MODE_0,

			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));

	}



	if (IS_GEN_RANGE(i915, 6, 7))

		intel_uncore_write(uncore, INSTPM,

				   _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

drivers/gpu/drm/i915/gt/intel_workarounds.c

+48 −2
Original line number Diff line number Diff line
@@ -1464,6 +1464,52 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			    GEN8_L3SQCREG4,

			    GEN8_LQSC_FLUSH_COHERENT_LINES);

	}



	if (IS_GEN(i915, 7))

		/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */

		wa_masked_en(wal,

			     GFX_MODE_GEN7,

			     GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);



	if (IS_GEN_RANGE(i915, 6, 7))

		/*

		 * We need to disable the AsyncFlip performance optimisations in

		 * order to use MI_WAIT_FOR_EVENT within the CS. It should

		 * already be programmed to '1' on all products.

		 *

		 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv

		 */

		wa_masked_en(wal,

			     MI_MODE,

			     ASYNC_FLIP_PERF_DISABLE);



	if (IS_GEN(i915, 6)) {

		/*

		 * Required for the hardware to program scanline values for

		 * waiting

		 * WaEnableFlushTlbInvalidationMode:snb

		 */

		wa_masked_en(wal,

			     GFX_MODE,

			     GFX_TLB_INVALIDATE_EXPLICIT);



		/*

		 * From the Sandybridge PRM, volume 1 part 3, page 24:

		 * "If this bit is set, STCunit will have LRA as replacement

		 *  policy. [...] This bit must be reset. LRA replacement

		 *  policy is not supported."

		 */

		wa_masked_dis(wal,

			      CACHE_MODE_0,

			      CM0_STC_EVICT_DISABLE_LRA_SNB);

	}



	if (IS_GEN_RANGE(i915, 4, 6))

		/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */

		wa_add(wal, MI_MODE,

		       0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),

		       /* XXX bit doesn't stick on Broadwater */

		       IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);

}



static void
@@ -1482,7 +1528,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
static void

engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)

{

	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))

	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))

		return;



	if (engine->class == RENDER_CLASS)
@@ -1495,7 +1541,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine) 
{

	struct i915_wa_list *wal = &engine->wa_list;



	if (INTEL_GEN(engine->i915) < 8)

	if (INTEL_GEN(engine->i915) < 4)

		return;



	wa_init_start(wal, "engine", engine->name);

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