Commit 37e88224 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-cleanups-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cleanups from Ingo Molnar:
 "Misc cleanups all around the place"

* tag 'x86-cleanups-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/ioperm: Initialize pointer bitmap with NULL rather than 0
  x86: uv: uv_hub.h: Delete duplicated word
  x86: cmpxchg_32.h: Delete duplicated word
  x86: bootparam.h: Delete duplicated word
  x86/mm: Remove the unused mk_kernel_pgd() #define
  x86/tsc: Remove unused "US_SCALE" and "NS_SCALE" leftover macros
  x86/ioapic: Remove unused "IOAPIC_AUTO" define
  x86/mm: Drop unused MAX_PHYSADDR_BITS
  x86/msr: Move the F15h MSRs where they belong
  x86/idt: Make idt_descr static
  initrd: Remove erroneous comment
  x86/mm/32: Fix -Wmissing prototypes warnings for init.c
  cpu/speculation: Add prototype for cpu_show_srbds()
  x86/mm: Fix -Wmissing-prototypes warnings for arch/x86/mm/init.c
  x86/asm: Unify __ASSEMBLY__ blocks
  x86/cpufeatures: Mark two free bits in word 3
  x86/msr: Lift AMD family 0x15 power-specific MSRs
parents 1ff9b20b 90fc7392

arch/x86/events/amd/power.c

+0 −4
Original line number Diff line number Diff line
@@ -13,10 +13,6 @@ 
#include <asm/cpu_device_id.h>

#include "../perf_event.h"



#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a

#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b

#define MSR_F15H_PTSC			0xc0010280



/* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */

#define AMD_POWER_EVENT_MASK		0xFFULL

arch/x86/include/asm/asm.h

+2 −4
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ 
	_ASM_PTR (entry);					\

	.popsection



#else

#else /* ! __ASSEMBLY__ */

# define _EXPAND_EXTABLE_HANDLE(x) #x

# define _ASM_EXTABLE_HANDLE(from, to, handler)			\

	" .pushsection \"__ex_table\",\"a\"\n"			\
@@ -164,9 +164,7 @@ 
	_ASM_EXTABLE_HANDLE(from, to, ex_handler_fault)



/* For C file, we already have NOKPROBE_SYMBOL macro */

#endif



#ifndef __ASSEMBLY__

/*

 * This output constraint should be used for any inline asm which has a "call"

 * instruction.  Otherwise the asm may be inserted before the frame pointer
@@ -175,6 +173,6 @@ 
 */

register unsigned long current_stack_pointer asm(_ASM_SP);

#define ASM_CALL_CONSTRAINT "+r" (current_stack_pointer)

#endif

#endif /* __ASSEMBLY__ */



#endif /* _ASM_X86_ASM_H */

arch/x86/include/asm/cmpxchg_32.h

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
#define _ASM_X86_CMPXCHG_32_H



/*

 * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you

 * Note: if you use set64_bit(), __cmpxchg64(), or their variants,

 *       you need to test for the feature in boot_cpu_data.

 */

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ 
#define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

/* free					( 3*32+17) */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
@@ -107,6 +108,7 @@ 
#define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */

#define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */

/* free					( 3*32+29) */

#define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */

#define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */

arch/x86/include/asm/io_apic.h

+0 −1
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ struct IR_IO_APIC_route_entry { 
struct irq_alloc_info;

struct ioapic_domain_cfg;



#define IOAPIC_AUTO			-1

#define IOAPIC_EDGE			0

#define IOAPIC_LEVEL			1

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