Commit 37b49f31 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-11-15' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Here is this weeks non-intel hw vuln fixes pull. Three drivers, all
  small fixes.

  i915:
   - MOCS table fixes for EHL and TGL
   - Update Display's rawclock on resume
   - GVT's dmabuf reference drop fix

  amdgpu:
   - Fix a potential crash in firmware parsing

  sun4i:
   - One fix to the dotclock dividers range for sun4i"

* tag 'drm-fixes-2019-11-15' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu: fix null pointer deref in firmware header printing
  drm/i915/tgl: MOCS table update
  Revert "drm/i915/ehl: Update MOCS table for EHL"
  drm/sun4i: tcon: Set min division of TCON0_DCLK to 1.
  drm/i915: update rawclk also on resume
  drm/i915/gvt: fix dropping obj reference twice
parents b4c0800e 07ceccac

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+16 −22
Original line number Diff line number Diff line
@@ -950,21 +950,7 @@ static void psp_print_fw_hdr(struct psp_context *psp, 
			     struct amdgpu_firmware_info *ucode)

{

	struct amdgpu_device *adev = psp->adev;

	const struct sdma_firmware_header_v1_0 *sdma_hdr =

		(const struct sdma_firmware_header_v1_0 *)

		adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;

	const struct gfx_firmware_header_v1_0 *ce_hdr =

		(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;

	const struct gfx_firmware_header_v1_0 *pfp_hdr =

		(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;

	const struct gfx_firmware_header_v1_0 *me_hdr =

		(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;

	const struct gfx_firmware_header_v1_0 *mec_hdr =

		(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	const struct rlc_firmware_header_v2_0 *rlc_hdr =

		(const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;

	const struct smc_firmware_header_v1_0 *smc_hdr =

		(const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;

	struct common_firmware_header *hdr;



	switch (ucode->ucode_id) {

	case AMDGPU_UCODE_ID_SDMA0:
@@ -975,25 +961,33 @@ static void psp_print_fw_hdr(struct psp_context *psp, 
	case AMDGPU_UCODE_ID_SDMA5:

	case AMDGPU_UCODE_ID_SDMA6:

	case AMDGPU_UCODE_ID_SDMA7:

		amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);

		hdr = (struct common_firmware_header *)

			adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;

		amdgpu_ucode_print_sdma_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_CP_CE:

		amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);

		hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;

		amdgpu_ucode_print_gfx_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_CP_PFP:

		amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);

		hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;

		amdgpu_ucode_print_gfx_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_CP_ME:

		amdgpu_ucode_print_gfx_hdr(&me_hdr->header);

		hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;

		amdgpu_ucode_print_gfx_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_CP_MEC1:

		amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);

		hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;

		amdgpu_ucode_print_gfx_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_RLC_G:

		amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);

		hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;

		amdgpu_ucode_print_rlc_hdr(hdr);

		break;

	case AMDGPU_UCODE_ID_SMC:

		amdgpu_ucode_print_smc_hdr(&smc_hdr->header);

		hdr = (struct common_firmware_header *)adev->pm.fw->data;

		amdgpu_ucode_print_smc_hdr(hdr);

		break;

	default:

		break;

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −0
Original line number Diff line number Diff line
@@ -4896,6 +4896,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) 


	power_domains->initializing = true;



	/* Must happen before power domain init on VLV/CHV */

	intel_update_rawclk(i915);



	if (INTEL_GEN(i915) >= 11) {

		icl_display_core_init(i915, resume);

	} else if (IS_CANNONLAKE(i915)) {

drivers/gpu/drm/i915/gt/intel_mocs.c

+1 −9
Original line number Diff line number Diff line
@@ -199,14 +199,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { 
	MOCS_ENTRY(15, \

		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \

		   L3_3_WB), \

	/* Bypass LLC - Uncached (EHL+) */ \

	MOCS_ENTRY(16, \

		   LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \

		   L3_1_UC), \

	/* Bypass LLC - L3 (Read-Only) (EHL+) */ \

	MOCS_ENTRY(17, \

		   LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \

		   L3_3_WB), \

	/* Self-Snoop - L3 + LLC */ \

	MOCS_ENTRY(18, \

		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
@@ -270,7 +262,7 @@ static const struct drm_i915_mocs_entry tigerlake_mocs_table[] = { 
		   L3_1_UC),

	/* HW Special Case (Displayable) */

	MOCS_ENTRY(61,

		   LE_1_UC | LE_TC_1_LLC | LE_SCF(1),

		   LE_1_UC | LE_TC_1_LLC,

		   L3_3_WB),

};

drivers/gpu/drm/i915/gvt/dmabuf.c

+2 −2
Original line number Diff line number Diff line
@@ -498,8 +498,6 @@ int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id) 
		goto out_free_gem;

	}



	i915_gem_object_put(obj);



	ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR);

	if (ret < 0) {

		gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
@@ -524,6 +522,8 @@ int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id) 
		    file_count(dmabuf->file),

		    kref_read(&obj->base.refcount));



	i915_gem_object_put(obj);



	return dmabuf_fd;



out_free_dmabuf:

drivers/gpu/drm/i915/i915_drv.c

+0 −3
Original line number Diff line number Diff line
@@ -364,9 +364,6 @@ static int i915_driver_modeset_probe(struct drm_device *dev) 
	if (ret)

		goto cleanup_vga_client;



	/* must happen before intel_power_domains_init_hw() on VLV/CHV */

	intel_update_rawclk(dev_priv);



	intel_power_domains_init_hw(dev_priv, false);



	intel_csr_ucode_init(dev_priv);

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