Commit 37a84ec6 authored by Seth Heasley's avatar Seth Heasley Committed by Jesse Barnes
Browse files

x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs 



This patch updates the Intel Ibex Peak (PCH) LPC and SMBus Controller
DeviceIDs.

The LPC Controller ID is set by Firmware within the range of
0x3b00-3b1f.  This range is included in pci_ids.h using min and max
values, and irq.c now has code to handle the range (in lieu of 32
additions to a SWITCH statement).

The SMBus Controller ID is a fixed-value and will not change.

Signed-off-by: default avatarSeth Heasley <seth.heasley@intel.com>
Acked-by: default avatarJean Delvare <khali@linux-fr.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent f7a10e32

arch/x86/pci/irq.c

+9 −2
Original line number Diff line number Diff line
@@ -590,13 +590,20 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route 
	case PCI_DEVICE_ID_INTEL_ICH10_1:

	case PCI_DEVICE_ID_INTEL_ICH10_2:

	case PCI_DEVICE_ID_INTEL_ICH10_3:

	case PCI_DEVICE_ID_INTEL_PCH_0:

	case PCI_DEVICE_ID_INTEL_PCH_1:

		r->name = "PIIX/ICH";

		r->get = pirq_piix_get;

		r->set = pirq_piix_set;

		return 1;

	}



	if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && 

		(device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {

		r->name = "PIIX/ICH";

		r->get = pirq_piix_get;

		r->set = pirq_piix_set;

		return 1;

	}



	return 0;

}

include/linux/pci_ids.h

+3 −3
Original line number Diff line number Diff line
@@ -2454,9 +2454,9 @@ 
#define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a

#define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30

#define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60

#define PCI_DEVICE_ID_INTEL_PCH_0	0x3b10

#define PCI_DEVICE_ID_INTEL_PCH_1	0x3b11

#define PCI_DEVICE_ID_INTEL_PCH_2	0x3b30

#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN	0x3b00

#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX	0x3b1f

#define PCI_DEVICE_ID_INTEL_PCH_SMBUS	0x3b30

#define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f

#define PCI_DEVICE_ID_INTEL_5100_16	0x65f0

#define PCI_DEVICE_ID_INTEL_5100_21	0x65f5

CRA Git | Maintained and supported by SUSTech CRA and CCSE