Commit 377e517b authored by Boris Brezillon's avatar Boris Brezillon Committed by Miquel Raynal
Browse files

mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg 



NAND datasheets usually give the maximum number of bad blocks per LUN
and this number can be used to help upper layers decide how much blocks
they should reserve for bad block handling.

Add a max_bad_eraseblocks_per_lun to the nand_memory_organization
struct and update the NAND_MEMORG() macro (and its users) accordingly.

We also provide a default mtd->_max_bad_blocks() implementation.

Signed-off-by: default avatarBoris Brezillon <bbrezillon@kernel.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
parent d090c250

drivers/mtd/nand/core.c

+34 −0
Original line number Diff line number Diff line
@@ -173,6 +173,40 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo) 
}

EXPORT_SYMBOL_GPL(nanddev_mtd_erase);



/**

 * nanddev_mtd_max_bad_blocks() - Get the maximum number of bad eraseblock on

 *				  a specific region of the NAND device

 * @mtd: MTD device

 * @offs: offset of the NAND region

 * @len: length of the NAND region

 *

 * Default implementation for mtd->_max_bad_blocks(). Only works if

 * nand->memorg.max_bad_eraseblocks_per_lun is > 0.

 *

 * Return: a positive number encoding the maximum number of eraseblocks on a

 * portion of memory, a negative error code otherwise.

 */

int nanddev_mtd_max_bad_blocks(struct mtd_info *mtd, loff_t offs, size_t len)

{

	struct nand_device *nand = mtd_to_nanddev(mtd);

	struct nand_pos pos, end;

	unsigned int max_bb = 0;



	if (!nand->memorg.max_bad_eraseblocks_per_lun)

		return -ENOTSUPP;



	nanddev_offs_to_pos(nand, offs, &pos);

	nanddev_offs_to_pos(nand, offs + len, &end);



	for (nanddev_offs_to_pos(nand, offs, &pos);

	     nanddev_pos_cmp(&pos, &end) < 0;

	     nanddev_pos_next_lun(nand, &pos))

		max_bb += nand->memorg.max_bad_eraseblocks_per_lun;



	return max_bb;

}

EXPORT_SYMBOL_GPL(nanddev_mtd_max_bad_blocks);



/**

 * nanddev_init() - Initialize a NAND device

 * @nand: NAND device

drivers/mtd/nand/spi/gigadevice.c

+4 −4
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = { 


static const struct spinand_info gigadevice_spinand_table[] = {

	SPINAND_INFO("GD5F1GQ4xA", 0xF1,

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -171,7 +171,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F2GQ4xA", 0xF2,

		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -180,7 +180,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F4GQ4xA", 0xF4,

		     NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -189,7 +189,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,

				     gd5fxgq4xa_ecc_get_status)),

	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

drivers/mtd/nand/spi/macronix.c

+2 −2
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, 


static const struct spinand_info macronix_spinand_table[] = {

	SPINAND_INFO("MX35LF1GE4AB", 0x12,

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 40, 1, 1, 1),

		     NAND_ECCREQ(4, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -109,7 +109,7 @@ static const struct spinand_info macronix_spinand_table[] = { 
		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,

				     mx35lf1ge4ab_ecc_get_status)),

	SPINAND_INFO("MX35LF2GE4AB", 0x22,

		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),

		     NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 2, 1, 1),

		     NAND_ECCREQ(4, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

drivers/mtd/nand/spi/micron.c

+1 −1
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand, 


static const struct spinand_info micron_spinand_table[] = {

	SPINAND_INFO("MT29F2G01ABAGD", 0x24,

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

drivers/mtd/nand/spi/toshiba.c

+6 −6
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, 
static const struct spinand_info toshiba_spinand_table[] = {

	/* 3.3V 1Gb */

	SPINAND_INFO("TC58CVG0S3", 0xC2,

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -106,7 +106,7 @@ static const struct spinand_info toshiba_spinand_table[] = { 
				     tc58cxgxsx_ecc_get_status)),

	/* 3.3V 2Gb */

	SPINAND_INFO("TC58CVG1S3", 0xCB,

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -116,7 +116,7 @@ static const struct spinand_info toshiba_spinand_table[] = { 
				     tc58cxgxsx_ecc_get_status)),

	/* 3.3V 4Gb */

	SPINAND_INFO("TC58CVG2S0", 0xCD,

		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),

		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -126,7 +126,7 @@ static const struct spinand_info toshiba_spinand_table[] = { 
				     tc58cxgxsx_ecc_get_status)),

	/* 1.8V 1Gb */

	SPINAND_INFO("TC58CYG0S3", 0xB2,

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -136,7 +136,7 @@ static const struct spinand_info toshiba_spinand_table[] = { 
				     tc58cxgxsx_ecc_get_status)),

	/* 1.8V 2Gb */

	SPINAND_INFO("TC58CYG1S3", 0xBB,

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,
@@ -146,7 +146,7 @@ static const struct spinand_info toshiba_spinand_table[] = { 
				     tc58cxgxsx_ecc_get_status)),

	/* 1.8V 4Gb */

	SPINAND_INFO("TC58CYG2S0", 0xBD,

		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),

		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,

					      &write_cache_variants,

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