Commit 377c0a94 authored by Kalle Valo's avatar Kalle Valo
Browse files
ath.git patches for v5.7. Major changes:

ath10k

* support for getting btcoex settings from Device Tree

* support QCA9377 SDIO device

ath11k

* add HE rate accounting

* add thermal sensor and cooling devices
parents ca44e47a dfb252c7
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+7 −0
Original line number Diff line number Diff line
@@ -91,6 +91,11 @@ Optional properties:
- qcom,msa-fixed-perm: Boolean context flag to disable SCM call for statically
		       mapped msa region.

- qcom,coexist-support : should contain eithr "0" or "1" to indicate coex
			 support by the hardware.
- qcom,coexist-gpio-pin : gpio pin number  information to support coex
			  which will be used by wifi firmware.

Example (to supply PCI based wifi block details):

In this example, the node is defined as child node of the PCI controller.
@@ -159,6 +164,8 @@ wifi0: wifi@a000000 {
	qcom,msi_addr = <0x0b006040>;
	qcom,msi_base = <0x40>;
	qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
	qcom,coexist-support = <1>;
	qcom,coexist-gpio-pin = <0x33>;
};

Example (to supply wcn3990 SoC wifi block details):
+81 −1
Original line number Diff line number Diff line
@@ -540,6 +540,33 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.fw_diag_ce_download = true,
		.tx_stats_over_pktlog = false,
	},
	{
		.id = QCA9377_HW_1_1_DEV_VERSION,
		.dev_id = QCA9377_1_0_DEVICE_ID,
		.bus = ATH10K_BUS_SDIO,
		.name = "qca9377 hw1.1 sdio",
		.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
		.uart_pin = 19,
		.otp_exe_param = 0,
		.channel_counters_freq_hz = 88000,
		.max_probe_resp_desc_thres = 0,
		.cal_data_len = 8124,
		.fw = {
			.dir = QCA9377_HW_1_0_FW_DIR,
			.board = QCA9377_HW_1_0_BOARD_DATA_FILE,
			.board_size = QCA9377_BOARD_DATA_SZ,
			.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
		},
		.hw_ops = &qca6174_ops,
		.hw_clk = qca6174_clk,
		.target_cpu_freq = 176000000,
		.decap_align_bytes = 4,
		.n_cipher_suites = 8,
		.num_peers = TARGET_QCA9377_HL_NUM_PEERS,
		.ast_skid_limit = 0x10,
		.num_wds_entries = 0x20,
		.uart_pin_workaround = true,
	},
	{
		.id = QCA4019_HW_1_0_DEV_VERSION,
		.dev_id = 0,
@@ -874,6 +901,13 @@ static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
		return -ENODATA;
	}

	if (ar->id.bmi_ids_valid) {
		ath10k_dbg(ar, ATH10K_DBG_BOOT,
			   "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
			   ar->id.bmi_board_id, ar->id.bmi_chip_id);
		goto skip_otp_download;
	}

	ath10k_dbg(ar, ATH10K_DBG_BOOT,
		   "boot upload otp to 0x%x len %zd for board id\n",
		   address, ar->normal_mode_fw.fw_file.otp_len);
@@ -921,6 +955,8 @@ static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
	ar->id.bmi_board_id = board_id;
	ar->id.bmi_chip_id = chip_id;

skip_otp_download:

	return 0;
}

@@ -2119,6 +2155,40 @@ done:
	return 0;
}

static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
{
	struct device_node *node;
	u8 coex_support = 0;
	int ret;

	node = ar->dev->of_node;
	if (!node)
		goto out;

	ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
	if (ret) {
		ar->coex_support = true;
		goto out;
	}

	if (coex_support) {
		ar->coex_support = true;
	} else {
		ar->coex_support = false;
		ar->coex_gpio_pin = -1;
		goto out;
	}

	ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
				   &ar->coex_gpio_pin);
	if (ret)
		ar->coex_gpio_pin = -1;

out:
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
		   ar->coex_support, ar->coex_gpio_pin);
}

static int ath10k_init_uart(struct ath10k *ar)
{
	int ret;
@@ -2696,14 +2766,22 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
		if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
			val |= WMI_10_4_BSS_CHANNEL_INFO_64;

		ath10k_core_fetch_btcoex_dt(ar);

		/* 10.4 firmware supports BT-Coex without reloading firmware
		 * via pdev param. To support Bluetooth coexistence pdev param,
		 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
		 * enabled always.
		 *
		 * We can still enable BTCOEX if firmware has the support
		 * eventhough btceox_support value is
		 * ATH10K_DT_BTCOEX_NOT_FOUND
		 */

		if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
		    test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
			     ar->running_fw->fw_file.fw_features))
			     ar->running_fw->fw_file.fw_features) &&
		    ar->coex_support)
			val |= WMI_10_4_COEX_GPIO_SUPPORT;

		if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
@@ -2863,6 +2941,8 @@ void ath10k_core_stop(struct ath10k *ar)
	ath10k_htt_tx_stop(&ar->htt);
	ath10k_htt_rx_free(&ar->htt);
	ath10k_wmi_detach(ar);

	ar->id.bmi_ids_valid = false;
}
EXPORT_SYMBOL(ath10k_core_stop);

+3 −0
Original line number Diff line number Diff line
@@ -1222,6 +1222,9 @@ struct ath10k {
	struct ath10k_bus_params bus_param;
	struct completion peer_delete_done;

	bool coex_support;
	int coex_gpio_pin;

	/* must be last */
	u8 drv_priv[0] __aligned(sizeof(void *));
};
+7 −5
Original line number Diff line number Diff line
@@ -1978,6 +1978,9 @@ static ssize_t ath10k_write_btcoex(struct file *file,
	if (strtobool(buf, &val) != 0)
		return -EINVAL;

	if (!ar->coex_support)
		return -EOPNOTSUPP;

	mutex_lock(&ar->conf_mutex);

	if (ar->state != ATH10K_STATE_ON &&
@@ -2370,9 +2373,6 @@ static ssize_t ath10k_write_warm_hw_reset(struct file *file,
		goto exit;
	}

	if (!(test_bit(WMI_SERVICE_RESET_CHIP, ar->wmi.svc_map)))
		ath10k_warn(ar, "wmi service for reset chip is not available\n");

	ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->pdev_reset,
					WMI_RST_MODE_WARM_RESET);

@@ -2647,7 +2647,9 @@ int ath10k_debug_register(struct ath10k *ar)
				    ar->debug.debugfs_phy, ar,
				    &fops_tpc_stats_final);

	debugfs_create_file("warm_hw_reset", 0600, ar->debug.debugfs_phy, ar,
	if (test_bit(WMI_SERVICE_RESET_CHIP, ar->wmi.svc_map))
		debugfs_create_file("warm_hw_reset", 0600,
				    ar->debug.debugfs_phy, ar,
				    &fops_warm_hw_reset);

	debugfs_create_file("ps_state_enable", 0600, ar->debug.debugfs_phy, ar,
+2 −1
Original line number Diff line number Diff line
@@ -2744,7 +2744,8 @@ static void ath10k_htt_rx_tx_compl_ind(struct ath10k *ar,
			continue;
		}

		tid = FIELD_GET(HTT_TX_PPDU_DUR_INFO0_TID_MASK, info0);
		tid = FIELD_GET(HTT_TX_PPDU_DUR_INFO0_TID_MASK, info0) &
						IEEE80211_QOS_CTL_TID_MASK;
		tx_duration = __le32_to_cpu(ppdu_dur->tx_duration);

		ieee80211_sta_register_airtime(peer->sta, tid, tx_duration, 0);
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