Commit 375faa93 authored by Pawel Moll's avatar Pawel Moll
Browse files

ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile 



This patch adds Device Tree file for the CoreTile Express
A15x2 A7x3 (V2P-CA15_CA7).

Note that the A7 cpu nodes are commented out, as the
big.LITTLE-relevant patches are not upstreamed yet. Till
this time one can use the board with two A15 cores only,
keeping the A7s in reset by adding the following setting
to the board.txt file in Versatile Express configuration
tree:

SCC: 0x018 0x00001FFF

Signed-off-by: default avatarPawel Moll <pawel.moll@arm.com>
parent 5f8f5a62

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

0 → 100644
+188 −0
Original line number Diff line number Diff line 
/*

 * ARM Ltd. Versatile Express

 *

 * CoreTile Express A15x2 A7x3

 * Cortex-A15_A7 MPCore (V2P-CA15_A7)

 *

 * HBI-0249A

 */



/dts-v1/;



/ {

	model = "V2P-CA15_CA7";

	arm,hbi = <0x249>;

	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	aliases {

		serial0 = &v2m_serial0;

		serial1 = &v2m_serial1;

		serial2 = &v2m_serial2;

		serial3 = &v2m_serial3;

		i2c0 = &v2m_i2c_dvi;

		i2c1 = &v2m_i2c_pcie;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <1>;

		};



/* A7s disabled till big.LITTLE patches are available...

		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x100>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x101>;

		};



		cpu4: cpu@4 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x102>;

		};

*/

	};



	memory@80000000 {

		device_type = "memory";

		reg = <0 0x80000000 0 0x40000000>;

	};



	wdt@2a490000 {

		compatible = "arm,sp805", "arm,primecell";

		reg = <0 0x2a490000 0 0x1000>;

		interrupts = <98>;

	};



	hdlcd@2b000000 {

		compatible = "arm,hdlcd";

		reg = <0 0x2b000000 0 0x1000>;

		interrupts = <0 85 4>;

	};



	memory-controller@2b0a0000 {

		compatible = "arm,pl341", "arm,primecell";

		reg = <0 0x2b0a0000 0 0x1000>;

	};



	gic: interrupt-controller@2c001000 {

		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0 0x2c001000 0 0x1000>,

		      <0 0x2c002000 0 0x1000>,

		      <0 0x2c004000 0 0x2000>,

		      <0 0x2c006000 0 0x2000>;

		interrupts = <1 9 0xf04>;

	};



	memory-controller@7ffd0000 {

		compatible = "arm,pl354", "arm,primecell";

		reg = <0 0x7ffd0000 0 0x1000>;

		interrupts = <0 86 4>,

			     <0 87 4>;

	};



	dma@7ff00000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0 0x7ff00000 0 0x1000>;

		interrupts = <0 92 4>,

			     <0 88 4>,

			     <0 89 4>,

			     <0 90 4>,

			     <0 91 4>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <1 13 0xf08>,

			     <1 14 0xf08>,

			     <1 11 0xf08>,

			     <1 10 0xf08>;

	};



	pmu {

		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";

		interrupts = <0 68 4>,

			     <0 69 4>;

	};



	motherboard {

		ranges = <0 0 0 0x08000000 0x04000000>,

			 <1 0 0 0x14000000 0x04000000>,

			 <2 0 0 0x18000000 0x04000000>,

			 <3 0 0 0x1c000000 0x04000000>,

			 <4 0 0 0x0c000000 0x04000000>,

			 <5 0 0 0x10000000 0x04000000>;



		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0  0 4>,

				<0 0  1 &gic 0  1 4>,

				<0 0  2 &gic 0  2 4>,

				<0 0  3 &gic 0  3 4>,

				<0 0  4 &gic 0  4 4>,

				<0 0  5 &gic 0  5 4>,

				<0 0  6 &gic 0  6 4>,

				<0 0  7 &gic 0  7 4>,

				<0 0  8 &gic 0  8 4>,

				<0 0  9 &gic 0  9 4>,

				<0 0 10 &gic 0 10 4>,

				<0 0 11 &gic 0 11 4>,

				<0 0 12 &gic 0 12 4>,

				<0 0 13 &gic 0 13 4>,

				<0 0 14 &gic 0 14 4>,

				<0 0 15 &gic 0 15 4>,

				<0 0 16 &gic 0 16 4>,

				<0 0 17 &gic 0 17 4>,

				<0 0 18 &gic 0 18 4>,

				<0 0 19 &gic 0 19 4>,

				<0 0 20 &gic 0 20 4>,

				<0 0 21 &gic 0 21 4>,

				<0 0 22 &gic 0 22 4>,

				<0 0 23 &gic 0 23 4>,

				<0 0 24 &gic 0 24 4>,

				<0 0 25 &gic 0 25 4>,

				<0 0 26 &gic 0 26 4>,

				<0 0 27 &gic 0 27 4>,

				<0 0 28 &gic 0 28 4>,

				<0 0 29 &gic 0 29 4>,

				<0 0 30 &gic 0 30 4>,

				<0 0 31 &gic 0 31 4>,

				<0 0 32 &gic 0 32 4>,

				<0 0 33 &gic 0 33 4>,

				<0 0 34 &gic 0 34 4>,

				<0 0 35 &gic 0 35 4>,

				<0 0 36 &gic 0 36 4>,

				<0 0 37 &gic 0 37 4>,

				<0 0 38 &gic 0 38 4>,

				<0 0 39 &gic 0 39 4>,

				<0 0 40 &gic 0 40 4>,

				<0 0 41 &gic 0 41 4>,

				<0 0 42 &gic 0 42 4>;

	};

};



/include/ "vexpress-v2m-rs1.dtsi"

arch/arm/mach-vexpress/Makefile.boot

+2 −1
Original line number Diff line number Diff line
@@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000 


dtb-$(CONFIG_ARCH_VEXPRESS_DT)	+= vexpress-v2p-ca5s.dtb \

				   vexpress-v2p-ca9.dtb \

				   vexpress-v2p-ca15-tc1.dtb
 
				   vexpress-v2p-ca15-tc1.dtb \

				   vexpress-v2p-ca15_a7.dtb

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