Commit 375981f2 authored by Girish K S's avatar Girish K S Committed by Mark Brown
Browse files

spi/s3c64xx: modified error interrupt handling and init 



The status of the interrupt is available in the status register,
so reading the clear pending register and writing back the same
value will not actually clear the pending interrupts. This patch
modifies the interrupt handler to read the status register and
clear the corresponding pending bit in the clear pending register.

Modified the hwInit function to clear all the pending interrupts.

Signed-off-by: default avatarGirish K S <ks.giri@samsung.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
parent b435ff21

drivers/spi/spi-s3c64xx.c

+25 −16
Original line number Diff line number Diff line
@@ -994,25 +994,30 @@ static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 
{

	struct s3c64xx_spi_driver_data *sdd = data;

	struct spi_master *spi = sdd->master;

	unsigned int val;

	unsigned int val, clr = 0;



	val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);

	val = readl(sdd->regs + S3C64XX_SPI_STATUS);



	val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |

		S3C64XX_SPI_PND_RX_UNDERRUN_CLR |

		S3C64XX_SPI_PND_TX_OVERRUN_CLR |

		S3C64XX_SPI_PND_TX_UNDERRUN_CLR;



	writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);



	if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)

	if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {

		clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;

		dev_err(&spi->dev, "RX overrun\n");

	if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)

	}

	if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {

		clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;

		dev_err(&spi->dev, "RX underrun\n");

	if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)

	}

	if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {

		clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;

		dev_err(&spi->dev, "TX overrun\n");

	if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)

	}

	if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {

		clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;

		dev_err(&spi->dev, "TX underrun\n");

	}



	/* Clear the pending irq by setting and then clearing it */

	writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);

	writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);



	return IRQ_HANDLED;

}
@@ -1036,9 +1041,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) 
	writel(0, regs + S3C64XX_SPI_MODE_CFG);

	writel(0, regs + S3C64XX_SPI_PACKET_CNT);



	/* Clear any irq pending bits */

	writel(readl(regs + S3C64XX_SPI_PENDING_CLR),

				regs + S3C64XX_SPI_PENDING_CLR);

	/* Clear any irq pending bits, should set and clear the bits */

	val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |

		S3C64XX_SPI_PND_RX_UNDERRUN_CLR |

		S3C64XX_SPI_PND_TX_OVERRUN_CLR |

		S3C64XX_SPI_PND_TX_UNDERRUN_CLR;

	writel(val, regs + S3C64XX_SPI_PENDING_CLR);

	writel(0, regs + S3C64XX_SPI_PENDING_CLR);



	writel(0, regs + S3C64XX_SPI_SWAP_CFG);

CRA Git | Maintained and supported by SUSTech CRA and CCSE