Commit 37448f7d authored by Eugene Surovegin's avatar Eugene Surovegin Committed by Jeff Garzik
Browse files

[PATCH] New PowerPC 4xx on-chip ethernet controller driver 



This patch replaces current PowerPC 4xx EMAC driver with
new, re-written from the scratch version. This patch is quite big
(~234K) because there is virtualy 0% of common code between old and
new version.

New driver uses NAPI, it solves stability problems under heavy packet
load and low memory, corrects chip register access and fixes numerous
small bugs I don't even remember now.

This patch has been tested on all supported in 2.6 PPC 4xx boards.
It's been used in production for almost a year now on custom
4xx hardware. PPC32 specific parts are already upstream.

Patch was acked by the current EMAC driver maintainer (Matt Porter). I
will be maintaining this new version.

Signed-off-by: default avatarEugene Surovegin <ebs@ebshome.net>
--

 Kconfig                   |   72
 ibm_emac/Makefile         |   13
 ibm_emac/ibm_emac.h       |  418 +++--
 ibm_emac/ibm_emac_core.c  | 3414 ++++++++++++++++++++++++----------------------
 ibm_emac/ibm_emac_core.h  |  313 ++--
 ibm_emac/ibm_emac_debug.c |  377 ++---
 ibm_emac/ibm_emac_debug.h |   63
 ibm_emac/ibm_emac_mal.c   |  674 +++++----
 ibm_emac/ibm_emac_mal.h   |  336 +++-
 ibm_emac/ibm_emac_phy.c   |  335 ++--
 ibm_emac/ibm_emac_phy.h   |  105 -
 ibm_emac/ibm_emac_rgmii.c |  201 ++
 ibm_emac/ibm_emac_rgmii.h |   68
 ibm_emac/ibm_emac_tah.c   |  111 +
 ibm_emac/ibm_emac_tah.h   |   96 -
 ibm_emac/ibm_emac_zmii.c  |  255 +++
 ibm_emac/ibm_emac_zmii.h  |  114 -
 17 files changed, 4114 insertions(+), 2851 deletions(-)
Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
parent b71b95ef

drivers/net/Kconfig

+54 −18
Original line number Diff line number Diff line
@@ -1163,38 +1163,74 @@ config IBMVETH 
	  be called ibmveth.



config IBM_EMAC

	bool "IBM PPC4xx EMAC driver support"

	tristate "PowerPC 4xx on-chip Ethernet support"

	depends on 4xx

	select CRC32

	---help---

	  This driver supports the IBM PPC4xx EMAC family of on-chip

	help

	  This driver supports the PowerPC 4xx EMAC family of on-chip

          Ethernet controllers.



config IBM_EMAC_ERRMSG

	bool "Verbose error messages"

	depends on IBM_EMAC && BROKEN



config IBM_EMAC_RXB

	int "Number of receive buffers"

	depends on IBM_EMAC

	default "128" if IBM_EMAC4

	default "64"

	default "128"



config IBM_EMAC_TXB

	int "Number of transmit buffers"

	depends on IBM_EMAC

	default "128" if IBM_EMAC4

	default "8"

	default "64"



config IBM_EMAC_POLL_WEIGHT

	int "MAL NAPI polling weight"

	depends on IBM_EMAC

	default "32"



config IBM_EMAC_FGAP

	int "Frame gap"

config IBM_EMAC_RX_COPY_THRESHOLD

	int "RX skb copy threshold (bytes)"

	depends on IBM_EMAC

	default "8"

	default "256"



config IBM_EMAC_SKBRES

	int "Skb reserve amount"

config IBM_EMAC_RX_SKB_HEADROOM

	int "Additional RX skb headroom (bytes)"

	depends on IBM_EMAC

	default "0"

	help

	  Additional receive skb headroom. Note, that driver

	  will always reserve at least 2 bytes to make IP header

	  aligned, so usualy there is no need to add any additional

	  headroom.

	  

	  If unsure, set to 0.



config IBM_EMAC_PHY_RX_CLK_FIX

	bool "PHY Rx clock workaround"

	depends on IBM_EMAC && (405EP || 440GX || 440EP)

	help

	  Enable this if EMAC attached to a PHY which doesn't generate

	  RX clock if there is no link, if this is the case, you will 

	  see "TX disable timeout" or "RX disable timeout" in the system

	  log.

	  

	  If unsure, say N.



config IBM_EMAC_DEBUG

	bool "Debugging"

	depends on IBM_EMAC

	default n



config IBM_EMAC_ZMII

	bool

	depends on IBM_EMAC && (NP405H || NP405L || 44x)

	default y



config IBM_EMAC_RGMII

	bool

	depends on IBM_EMAC && 440GX

	default y

		

config IBM_EMAC_TAH

	bool

	depends on IBM_EMAC && 440GX

	default y



config NET_PCI

	bool "EISA, VLB, PCI and on board controllers"

drivers/net/ibm_emac/Makefile

+6 −7
Original line number Diff line number Diff line 
#

# Makefile for the IBM PPC4xx EMAC controllers

# Makefile for the PowerPC 4xx on-chip ethernet driver

#



obj-$(CONFIG_IBM_EMAC) += ibm_emac.o



ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o 



# Only need this if you want to see additional debug messages

ifeq ($(CONFIG_IBM_EMAC_ERRMSG), y)

ibm_emac-objs += ibm_emac_debug.o

endif
 
ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o

ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o

ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o

ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o

drivers/net/ibm_emac/ibm_emac.h

+225 −183
Original line number Diff line number Diff line 
/*

 * ibm_emac.h

 * drivers/net/ibm_emac/ibm_emac.h

 *

 * Register definitions for PowerPC 4xx on-chip ethernet contoller

 *

 *      Armin Kuster akuster@mvista.com

 *      June, 2002

 * Copyright (c) 2004, 2005 Zultys Technologies.

 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>

 *

 * Copyright 2002 MontaVista Softare Inc.

 * Based on original work by

 *      Matt Porter <mporter@kernel.crashing.org>

 *      Armin Kuster <akuster@mvista.com>

 * 	Copyright 2002-2004 MontaVista Software Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 *

 */

#ifndef __IBM_EMAC_H_

#define __IBM_EMAC_H_



#include <linux/config.h>

#include <linux/types.h>



/* This is a simple check to prevent use of this driver on non-tested SoCs */

#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \

    !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \

    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H)

#error	"Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"

#endif



#ifndef _IBM_EMAC_H_

#define _IBM_EMAC_H_

/* General defines needed for the driver */

/* EMAC registers 		Write Access rules */

struct emac_regs {

	u32 mr0;		/* special 	*/

	u32 mr1;		/* Reset 	*/

	u32 tmr0;		/* special 	*/

	u32 tmr1;		/* special 	*/

	u32 rmr;		/* Reset 	*/

	u32 isr;		/* Always 	*/

	u32 iser;		/* Reset 	*/

	u32 iahr;		/* Reset, R, T 	*/

	u32 ialr;		/* Reset, R, T 	*/

	u32 vtpid;		/* Reset, R, T 	*/

	u32 vtci;		/* Reset, R, T 	*/

	u32 ptr;		/* Reset,    T 	*/

	u32 iaht1;		/* Reset, R	*/

	u32 iaht2;		/* Reset, R	*/

	u32 iaht3;		/* Reset, R	*/

	u32 iaht4;		/* Reset, R	*/

	u32 gaht1;		/* Reset, R	*/

	u32 gaht2;		/* Reset, R	*/

	u32 gaht3;		/* Reset, R	*/

	u32 gaht4;		/* Reset, R	*/

	u32 lsah;

	u32 lsal;

	u32 ipgvr;		/* Reset,    T 	*/

	u32 stacr;		/* special 	*/

	u32 trtr;		/* special 	*/

	u32 rwmr;		/* Reset 	*/

	u32 octx;

	u32 ocrx;

	u32 ipcr;

};



#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_ETHTOOL_REGS_VER		0

#define EMAC_ETHTOOL_REGS_SIZE		(sizeof(struct emac_regs) - sizeof(u32))

#else

#define EMAC_ETHTOOL_REGS_VER		1

#define EMAC_ETHTOOL_REGS_SIZE		sizeof(struct emac_regs)

#endif



/* Emac */

typedef struct emac_regs {

	u32 em0mr0;

	u32 em0mr1;

	u32 em0tmr0;

	u32 em0tmr1;

	u32 em0rmr;

	u32 em0isr;

	u32 em0iser;

	u32 em0iahr;

	u32 em0ialr;

	u32 em0vtpid;

	u32 em0vtci;

	u32 em0ptr;

	u32 em0iaht1;

	u32 em0iaht2;

	u32 em0iaht3;

	u32 em0iaht4;

	u32 em0gaht1;

	u32 em0gaht2;

	u32 em0gaht3;

	u32 em0gaht4;

	u32 em0lsah;

	u32 em0lsal;

	u32 em0ipgvr;

	u32 em0stacr;

	u32 em0trtr;

	u32 em0rwmr;

} emac_t;

/* EMACx_MR0 */

#define EMAC_MR0_RXI			0x80000000

#define EMAC_MR0_TXI			0x40000000

#define EMAC_MR0_SRST			0x20000000

#define EMAC_MR0_TXE			0x10000000

#define EMAC_MR0_RXE			0x08000000

#define EMAC_MR0_WKE			0x04000000



/* MODE REG 0 */

#define EMAC_M0_RXI			0x80000000

#define EMAC_M0_TXI			0x40000000

#define EMAC_M0_SRST			0x20000000

#define EMAC_M0_TXE			0x10000000

#define EMAC_M0_RXE			0x08000000

#define EMAC_M0_WKE			0x04000000

/* EMACx_MR1 */

#define EMAC_MR1_FDE			0x80000000

#define EMAC_MR1_ILE			0x40000000

#define EMAC_MR1_VLE			0x20000000

#define EMAC_MR1_EIFC			0x10000000

#define EMAC_MR1_APP			0x08000000

#define EMAC_MR1_IST			0x01000000



/* MODE Reg 1 */

#define EMAC_M1_FDE			0x80000000

#define EMAC_M1_ILE			0x40000000

#define EMAC_M1_VLE			0x20000000

#define EMAC_M1_EIFC			0x10000000

#define EMAC_M1_APP			0x08000000

#define EMAC_M1_AEMI			0x02000000

#define EMAC_M1_IST			0x01000000

#define EMAC_M1_MF_1000GPCS		0x00c00000	/* Internal GPCS */

#define EMAC_M1_MF_1000MBPS		0x00800000	/* External GPCS */

#define EMAC_M1_MF_100MBPS		0x00400000

#define EMAC_M1_RFS_16K                 0x00280000	/* 000 for 512 byte */

#define EMAC_M1_TR			0x00008000

#ifdef CONFIG_IBM_EMAC4

#define EMAC_M1_RFS_8K                  0x00200000

#define EMAC_M1_RFS_4K                  0x00180000

#define EMAC_M1_RFS_2K                  0x00100000

#define EMAC_M1_RFS_1K                  0x00080000

#define EMAC_M1_TX_FIFO_16K             0x00050000	/* 0's for 512 byte */

#define EMAC_M1_TX_FIFO_8K              0x00040000

#define EMAC_M1_TX_FIFO_4K              0x00030000

#define EMAC_M1_TX_FIFO_2K              0x00020000

#define EMAC_M1_TX_FIFO_1K              0x00010000

#define EMAC_M1_TX_TR                   0x00008000

#define EMAC_M1_TX_MWSW                 0x00001000	/* 0 wait for status */

#define EMAC_M1_JUMBO_ENABLE            0x00000800	/* Upt to 9Kr status */

#define EMAC_M1_OPB_CLK_66              0x00000008	/* 66Mhz */

#define EMAC_M1_OPB_CLK_83              0x00000010	/* 83Mhz */

#define EMAC_M1_OPB_CLK_100             0x00000018	/* 100Mhz */

#define EMAC_M1_OPB_CLK_100P            0x00000020	/* 100Mhz+ */

#else				/* CONFIG_IBM_EMAC4 */

#define EMAC_M1_RFS_4K			0x00300000	/* ~4k for 512 byte */

#define EMAC_M1_RFS_2K			0x00200000

#define EMAC_M1_RFS_1K			0x00100000

#define EMAC_M1_TX_FIFO_2K		0x00080000	/* 0's for 512 byte */

#define EMAC_M1_TX_FIFO_1K		0x00040000

#define EMAC_M1_TR0_DEPEND		0x00010000	/* 0'x for single packet */

#define EMAC_M1_TR1_DEPEND		0x00004000

#define EMAC_M1_TR1_MULTI		0x00002000

#define EMAC_M1_JUMBO_ENABLE		0x00001000

#endif				/* CONFIG_IBM_EMAC4 */

#define EMAC_M1_BASE			(EMAC_M1_TX_FIFO_2K | \

					EMAC_M1_APP | \

					EMAC_M1_TR | EMAC_M1_VLE)

#define EMAC_MR1_MF_MASK		0x00c00000

#define EMAC_MR1_MF_10			0x00000000

#define EMAC_MR1_MF_100			0x00400000

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_MR1_MF_1000		0x00000000

#define EMAC_MR1_MF_1000GPCS		0x00000000

#define EMAC_MR1_MF_IPPA(id)		0x00000000

#else

#define EMAC_MR1_MF_1000		0x00800000

#define EMAC_MR1_MF_1000GPCS		0x00c00000

#define EMAC_MR1_MF_IPPA(id)		(((id) & 0x1f) << 6)

#endif



#define EMAC_TX_FIFO_SIZE		2048



#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_MR1_RFS_4K			0x00300000

#define EMAC_MR1_RFS_16K		0x00000000

#define EMAC_RX_FIFO_SIZE(gige)		4096

#define EMAC_MR1_TFS_2K			0x00080000

#define EMAC_MR1_TR0_MULT		0x00008000

#define EMAC_MR1_JPSM			0x00000000

#define EMAC_MR1_BASE(opb)		(EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)

#else

#define EMAC_MR1_RFS_4K			0x00180000

#define EMAC_MR1_RFS_16K		0x00280000

#define EMAC_RX_FIFO_SIZE(gige)		((gige) ? 16384 : 4096)

#define EMAC_MR1_TFS_2K			0x00020000

#define EMAC_MR1_TR			0x00008000

#define EMAC_MR1_MWSW_001		0x00001000

#define EMAC_MR1_JPSM			0x00000800

#define EMAC_MR1_OBCI_MASK		0x00000038

#define EMAC_MR1_OBCI_50		0x00000000

#define EMAC_MR1_OBCI_66		0x00000008

#define EMAC_MR1_OBCI_83		0x00000010

#define EMAC_MR1_OBCI_100		0x00000018

#define EMAC_MR1_OBCI_100P		0x00000020

#define EMAC_MR1_OBCI(freq)		((freq) <= 50  ? EMAC_MR1_OBCI_50 : \

					 (freq) <= 66  ? EMAC_MR1_OBCI_66 : \

					 (freq) <= 83  ? EMAC_MR1_OBCI_83 : \

					 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)

#define EMAC_MR1_BASE(opb)		(EMAC_MR1_TFS_2K | EMAC_MR1_TR | \

					 EMAC_MR1_MWSW_001 | EMAC_MR1_OBCI(opb))

#endif



/* Transmit Mode Register 0 */

#define EMAC_TMR0_GNP0			0x80000000

#define EMAC_TMR0_GNP1			0x40000000

#define EMAC_TMR0_GNPD			0x20000000

#define EMAC_TMR0_FC			0x10000000

/* EMACx_TMR0 */

#define EMAC_TMR0_GNP			0x80000000

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_TMR0_DEFAULT		0x00000000	

#else

#define EMAC_TMR0_TFAE_2_32		0x00000001

#define EMAC_TMR0_TFAE_4_64		0x00000002

#define EMAC_TMR0_TFAE_8_128		0x00000003
@@ -112,14 +144,36 @@ typedef struct emac_regs { 
#define EMAC_TMR0_TFAE_32_512		0x00000005

#define EMAC_TMR0_TFAE_64_1024		0x00000006

#define EMAC_TMR0_TFAE_128_2048		0x00000007

#define EMAC_TMR0_DEFAULT		EMAC_TMR0_TFAE_2_32

#endif

#define EMAC_TMR0_XMIT			(EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)



/* EMACx_TMR1 */



/* IBM manuals are not very clear here. 

 * This is my interpretation of how things are. --ebs

 */

#if defined(CONFIG_40x)

#define EMAC_FIFO_ENTRY_SIZE		8

#define EMAC_MAL_BURST_SIZE		(16 * 4)

#else

#define EMAC_FIFO_ENTRY_SIZE		16

#define EMAC_MAL_BURST_SIZE		(64 * 4)

#endif



#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_TMR1(l,h)			(((l) << 27) | (((h) & 0xff) << 16))

#else

#define EMAC_TMR1(l,h)			(((l) << 27) | (((h) & 0x3ff) << 14))

#endif



/* Receive Mode Register */

/* EMACx_RMR */

#define EMAC_RMR_SP			0x80000000

#define EMAC_RMR_SFCS			0x40000000

#define EMAC_RMR_ARRP			0x20000000

#define EMAC_RMR_ARP			0x10000000

#define EMAC_RMR_AROP			0x08000000

#define EMAC_RMR_ARPI			0x04000000

#define EMAC_RMR_RRP			0x20000000

#define EMAC_RMR_RFP			0x10000000

#define EMAC_RMR_ROP			0x08000000

#define EMAC_RMR_RPIR			0x04000000

#define EMAC_RMR_PPP			0x02000000

#define EMAC_RMR_PME			0x01000000

#define EMAC_RMR_PMME			0x00800000
@@ -127,6 +181,9 @@ typedef struct emac_regs { 
#define EMAC_RMR_MIAE			0x00200000

#define EMAC_RMR_BAE			0x00100000

#define EMAC_RMR_MAE			0x00080000

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_RMR_BASE			0x00000000

#else

#define EMAC_RMR_RFAF_2_32		0x00000001

#define EMAC_RMR_RFAF_4_64		0x00000002

#define EMAC_RMR_RFAF_8_128		0x00000003
@@ -134,9 +191,21 @@ typedef struct emac_regs { 
#define EMAC_RMR_RFAF_32_512		0x00000005

#define EMAC_RMR_RFAF_64_1024		0x00000006

#define EMAC_RMR_RFAF_128_2048		0x00000007

#define EMAC_RMR_BASE			(EMAC_RMR_IAE | EMAC_RMR_BAE)

#define EMAC_RMR_BASE			EMAC_RMR_RFAF_128_2048

#endif



/* Interrupt Status & enable Regs */

/* EMACx_ISR & EMACx_ISER */

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_ISR_TXPE			0x00000000

#define EMAC_ISR_RXPE			0x00000000

#define EMAC_ISR_TXUE			0x00000000

#define EMAC_ISR_RXOE			0x00000000

#else

#define EMAC_ISR_TXPE			0x20000000

#define EMAC_ISR_RXPE			0x10000000

#define EMAC_ISR_TXUE			0x08000000

#define EMAC_ISR_RXOE			0x04000000

#endif

#define EMAC_ISR_OVR			0x02000000

#define EMAC_ISR_PP			0x01000000

#define EMAC_ISR_BP			0x00800000
@@ -147,53 +216,62 @@ typedef struct emac_regs { 
#define EMAC_ISR_PTLE			0x00040000

#define EMAC_ISR_ORE			0x00020000

#define EMAC_ISR_IRE			0x00010000

#define EMAC_ISR_DBDM			0x00000200

#define EMAC_ISR_DB0			0x00000100

#define EMAC_ISR_SE0			0x00000080

#define EMAC_ISR_TE0			0x00000040

#define EMAC_ISR_DB1			0x00000020

#define EMAC_ISR_SE1			0x00000010

#define EMAC_ISR_TE1			0x00000008

#define EMAC_ISR_SQE			0x00000080

#define EMAC_ISR_TE			0x00000040

#define EMAC_ISR_MOS			0x00000002

#define EMAC_ISR_MOF			0x00000001



/* STA CONTROL REG */

/* EMACx_STACR */

#define EMAC_STACR_PHYD_MASK		0xffff

#define EMAC_STACR_PHYD_SHIFT		16

#define EMAC_STACR_OC			0x00008000

#define EMAC_STACR_PHYE			0x00004000

#define EMAC_STACR_WRITE		0x00002000

#define EMAC_STACR_READ			0x00001000

#define EMAC_STACR_CLK_83MHZ		0x00000800	/* 0's for 50Mhz */

#define EMAC_STACR_CLK_66MHZ		0x00000400

#define EMAC_STACR_CLK_100MHZ		0x00000C00

#define EMAC_STACR_STAC_MASK		0x00003000

#define EMAC_STACR_STAC_READ		0x00001000

#define EMAC_STACR_STAC_WRITE		0x00002000

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_STACR_OPBC_MASK		0x00000C00

#define EMAC_STACR_OPBC_50		0x00000000

#define EMAC_STACR_OPBC_66		0x00000400

#define EMAC_STACR_OPBC_83		0x00000800

#define EMAC_STACR_OPBC_100		0x00000C00

#define EMAC_STACR_OPBC(freq)		((freq) <= 50 ? EMAC_STACR_OPBC_50 : \

					 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \

					 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)

#define EMAC_STACR_BASE(opb)		EMAC_STACR_OPBC(opb)

#else

#define EMAC_STACR_BASE(opb)		0x00000000

#endif

#define EMAC_STACR_PCDA_MASK		0x1f

#define EMAC_STACR_PCDA_SHIFT		5

#define EMAC_STACR_PRA_MASK		0x1f



/* Transmit Request Threshold Register */

#define EMAC_TRTR_1600			0x18000000	/* 0's for 64 Bytes */

#define EMAC_TRTR_1024			0x0f000000

#define EMAC_TRTR_512			0x07000000

#define EMAC_TRTR_256			0x03000000

#define EMAC_TRTR_192			0x10000000

#define EMAC_TRTR_128			0x01000000

/* EMACx_TRTR */

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_TRTR_SHIFT			27

#else

#define EMAC_TRTR_SHIFT			24

#endif

#define EMAC_TRTR(size)			((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)



/* EMACx_RWMR */

#if !defined(CONFIG_IBM_EMAC4)

#define EMAC_RWMR(l,h)			(((l) << 23) | ( ((h) & 0x1ff) << 7))	

#else

#define EMAC_RWMR(l,h)			(((l) << 22) | ( ((h) & 0x3ff) << 6))	

#endif



/* EMAC specific TX descriptor control fields (write access) */

#define EMAC_TX_CTRL_GFCS		0x0200

#define EMAC_TX_CTRL_GP			0x0100

#define EMAC_TX_CTRL_ISA		0x0080

#define EMAC_TX_CTRL_RSA		0x0040

#define EMAC_TX_CTRL_IVT		0x0020

#define EMAC_TX_CTRL_RVT		0x0010

#define EMAC_TX_CTRL_TAH_CSUM		0x000e	/* TAH only */

#define EMAC_TX_CTRL_TAH_SEG4		0x000a	/* TAH only */

#define EMAC_TX_CTRL_TAH_SEG3		0x0008	/* TAH only */

#define EMAC_TX_CTRL_TAH_SEG2		0x0006	/* TAH only */

#define EMAC_TX_CTRL_TAH_SEG1		0x0004	/* TAH only */

#define EMAC_TX_CTRL_TAH_SEG0		0x0002	/* TAH only */

#define EMAC_TX_CTRL_TAH_DIS		0x0000	/* TAH only */



#define EMAC_TX_CTRL_DFLT ( \

	MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )

#define EMAC_TX_CTRL_TAH_CSUM		0x000e



/* madmal transmit status / Control bits */

/* EMAC specific TX descriptor status fields (read access) */

#define EMAC_TX_ST_BFCS			0x0200

#define EMAC_TX_ST_BPP			0x0100

#define EMAC_TX_ST_LCS			0x0080

#define EMAC_TX_ST_ED			0x0040

#define EMAC_TX_ST_EC			0x0020
@@ -202,8 +280,16 @@ typedef struct emac_regs { 
#define EMAC_TX_ST_SC			0x0004

#define EMAC_TX_ST_UR			0x0002

#define EMAC_TX_ST_SQE			0x0001

#if !defined(CONFIG_IBM_EMAC_TAH)

#define EMAC_IS_BAD_TX(v)		((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \

					 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \

					 EMAC_TX_ST_MC | EMAC_TX_ST_UR))

#else

#define EMAC_IS_BAD_TX(v)		((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \

					 EMAC_TX_ST_EC | EMAC_TX_ST_LC))

#endif					 



/* madmal receive status / Control bits */

/* EMAC specific RX descriptor status fields (read access) */

#define EMAC_RX_ST_OE			0x0200

#define EMAC_RX_ST_PP			0x0100

#define EMAC_RX_ST_BP			0x0080
@@ -214,54 +300,10 @@ typedef struct emac_regs { 
#define EMAC_RX_ST_PTL			0x0004

#define EMAC_RX_ST_ORE			0x0002

#define EMAC_RX_ST_IRE			0x0001

#define EMAC_BAD_RX_PACKET		0x02ff

#define EMAC_CSUM_VER_ERROR		0x0003



/* identify a bad rx packet dependent on emac features */

#ifdef CONFIG_IBM_EMAC4

#define EMAC_IS_BAD_RX_PACKET(desc) \

	(((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \

	((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \

	((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))

#else

#define EMAC_IS_BAD_RX_PACKET(desc) \

	 (desc & EMAC_BAD_RX_PACKET)

#endif



/* SoC implementation specific EMAC register defaults */

#if defined(CONFIG_440GP)

#define EMAC_RWMR_DEFAULT		0x80009000

#define EMAC_TMR0_DEFAULT		0x00000000

#define EMAC_TMR1_DEFAULT		0xf8640000

#elif defined(CONFIG_440GX)

#define EMAC_RWMR_DEFAULT		0x1000a200

#define EMAC_TMR0_DEFAULT		EMAC_TMR0_TFAE_2_32

#define EMAC_TMR1_DEFAULT		0xa00f0000

#elif defined(CONFIG_440SP)

#define EMAC_RWMR_DEFAULT		0x08002000

#define EMAC_TMR0_DEFAULT		EMAC_TMR0_TFAE_128_2048

#define EMAC_TMR1_DEFAULT		0xf8200000

#else

#define EMAC_RWMR_DEFAULT		0x0f002000

#define EMAC_TMR0_DEFAULT		0x00000000

#define EMAC_TMR1_DEFAULT		0x380f0000

#endif				/* CONFIG_440GP */



/* Revision specific EMAC register defaults */

#ifdef CONFIG_IBM_EMAC4

#define EMAC_M1_DEFAULT			(EMAC_M1_BASE | \

					EMAC_M1_OPB_CLK_83 | \

					EMAC_M1_TX_MWSW)

#define EMAC_RMR_DEFAULT		(EMAC_RMR_BASE | \

					EMAC_RMR_RFAF_128_2048)

#define EMAC_TMR0_XMIT			(EMAC_TMR0_GNP0 | \

					EMAC_TMR0_DEFAULT)

#define EMAC_TRTR_DEFAULT		EMAC_TRTR_1024

#else				/* !CONFIG_IBM_EMAC4 */

#define EMAC_M1_DEFAULT			EMAC_M1_BASE

#define EMAC_RMR_DEFAULT		EMAC_RMR_BASE

#define EMAC_TMR0_XMIT			EMAC_TMR0_GNP0

#define EMAC_TRTR_DEFAULT		EMAC_TRTR_1600

#endif				/* CONFIG_IBM_EMAC4 */



#endif
 
#define EMAC_RX_TAH_BAD_CSUM		0x0003

#define EMAC_BAD_RX_MASK		(EMAC_RX_ST_OE | EMAC_RX_ST_BP | \

					 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \

					 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \

					 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \

					 EMAC_RX_ST_IRE )

#endif /* __IBM_EMAC_H_ */

drivers/net/ibm_emac/ibm_emac_core.c

+1804 −1598

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drivers/net/ibm_emac/ibm_emac_core.h

+194 −119

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