net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap (37144476) · Commits · 戴 / test

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)). There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY. Implement driver support for device-tree property meant to advertise the wrong strapping. [1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf Signed-off-by:

Murali Karicheri <m-karicheri2@ti.com> [nsekhar@ti.com: rebase to mainline, code simplification] Signed-off-by:

Sekhar Nori <nsekhar@ti.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/phy/dp83867.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -91,6 +91,7 @@ struct dp83867_private {
		int fifo_depth;
		int io_impedance;
		int port_mirroring;
		bool rxctrl_strap_quirk;
		};

		static int dp83867_ack_interrupt(struct phy_device *phydev)
		@@ -164,6 +165,9 @@ static int dp83867_of_init(struct phy_device *phydev)
		else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;

		dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
		"ti,dp83867-rxctrl-strap-quirk");

		ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
		&dp83867->rx_id_delay);
		if (ret &&
		@@ -214,6 +218,13 @@ static int dp83867_config_init(struct phy_device *phydev)
		dp83867 = (struct dp83867_private *)phydev->priv;
		}

		/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
		if (dp83867->rxctrl_strap_quirk) {
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
		val &= ~BIT(7);
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
		}

		if (phy_interface_is_rgmii(phydev)) {
		val = phy_read(phydev, MII_DP83867_PHYCTRL);
		if (val < 0)

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