Commit 36e9e1ea authored by Suresh Siddha's avatar Suresh Siddha Committed by Ingo Molnar
Browse files

x86: Handle legacy PIC interrupts on all the cpu's 



Ingo Molnar reported that with the recent changes of not
statically blocking IRQ0_VECTOR..IRQ15_VECTOR's on all the
cpu's, broke an AMD platform (with Nvidia chipset) boot when
"noapic" boot option is used.

On this platform, legacy PIC interrupts are getting delivered to
all the cpu's instead of just the boot cpu. Thus not
initializing the vector to irq mapping for the legacy irq's
resulted in not handling certain interrupts causing boot hang.

Fix this by initializing the vector to irq mapping on all the
logical cpu's, if the legacy IRQ is handled by the legacy PIC.

Reported-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
[ -v2: io-apic-enabled improvement ]
Acked-by: default avatarYinghai Lu <yinghai@kernel.org>
Cc: Eric W. Biederman <ebiederm@xmission.com>
LKML-Reference: <1268692386.3296.43.camel@sbs-t61.sc.intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent a3d3203e

arch/x86/include/asm/hw_irq.h

+1 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ extern void (*__initconst interrupt[NR_VECTORS-FIRST_EXTERNAL_VECTOR])(void); 


typedef int vector_irq_t[NR_VECTORS];

DECLARE_PER_CPU(vector_irq_t, vector_irq);

extern void setup_vector_irq(int cpu);



#ifdef CONFIG_X86_IO_APIC

extern void lock_vector_lock(void);

arch/x86/kernel/apic/io_apic.c

+8 −0
Original line number Diff line number Diff line
@@ -1268,6 +1268,14 @@ void __setup_vector_irq(int cpu) 
	/* Mark the inuse vectors */

	for_each_irq_desc(irq, desc) {

		cfg = desc->chip_data;



		/*

		 * If it is a legacy IRQ handled by the legacy PIC, this cpu

		 * will be part of the irq_cfg's domain.

		 */

		if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))

			cpumask_set_cpu(cpu, cfg->domain);



		if (!cpumask_test_cpu(cpu, cfg->domain))

			continue;

		vector = cfg->vector;

arch/x86/kernel/irqinit.c

+22 −0
Original line number Diff line number Diff line
@@ -141,6 +141,28 @@ void __init init_IRQ(void) 
	x86_init.irqs.intr_init();

}



/*

 * Setup the vector to irq mappings.

 */

void setup_vector_irq(int cpu)

{

#ifndef CONFIG_X86_IO_APIC

	int irq;



	/*

	 * On most of the platforms, legacy PIC delivers the interrupts on the

	 * boot cpu. But there are certain platforms where PIC interrupts are

	 * delivered to multiple cpu's. If the legacy IRQ is handled by the

	 * legacy PIC, for the new cpu that is coming online, setup the static

	 * legacy vector to irq mapping:

	 */

	for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)

		per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;

#endif



	__setup_vector_irq(cpu);

}



static void __init smp_intr_init(void)

{

#ifdef CONFIG_SMP

arch/x86/kernel/smpboot.c

+1 −1
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ static void __cpuinit smp_callin(void) 
	/*

	 * Need to setup vector mappings before we enable interrupts.

	 */

	__setup_vector_irq(smp_processor_id());

	setup_vector_irq(smp_processor_id());

	/*

	 * Get our bogomips.

	 *

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