Commit 36e7999d authored by Eric Anholt's avatar Eric Anholt
Browse files

drm/v3d: Document cache flushing ABI. 



Right now, userspace doesn't do any L2T writes, but we should lay out
our expectations for how it works.

v2: Explicitly mention the VCD cache flushing requirements and that
    we'll flush the other caches before each of the CLs.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203222438.25417-1-eric@anholt.net


Reviewed-by: default avatarDave Emett <david.emett@broadcom.com>
parent dd847a70

include/uapi/drm/v3d_drm.h

+8 −0
Original line number Diff line number Diff line
@@ -52,6 +52,14 @@ extern "C" { 
 *

 * This asks the kernel to have the GPU execute an optional binner

 * command list, and a render command list.

 *

 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before

 * each CL executes.  The VCD cache should be flushed (if necessary)

 * by the submitted CLs.  The TLB writes are guaranteed to have been

 * flushed by the time the render done IRQ happens, which is the

 * trigger for out_sync.  Any dirtying of cachelines by the job (only

 * possible using TMU writes) must be flushed by the caller using the

 * CL's cache flush commands.

 */

struct drm_v3d_submit_cl {

	/* Pointer to the binner command list.

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