xtensa: fix TLB sanity checker (36de10c4) · Commits · 戴 / test

Virtual and translated addresses retrieved by the xtensa TLB sanity checker must be consistent, i.e. correspond to the same state of the checked TLB entry. KASAN shadow memory is mapped dynamically using auto-refill TLB entries and thus may change TLB state between the virtual and translated address retrieval, resulting in false TLB insanity report. Move read_xtlb_translation close to read_xtlb_virtual to make sure that read values are consistent. Cc: stable@vger.kernel.org Fixes: ("xtensa: check TLB sanity on return to userspace") Signed-off-by:

Max Filippov <jcmvbkbc@gmail.com>

arch/xtensa/mm/tlb.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -224,6 +224,8 @@ static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
		unsigned tlbidx = w \| (e << PAGE_SHIFT);
		unsigned r0 = dtlb ?
		read_dtlb_virtual(tlbidx) : read_itlb_virtual(tlbidx);
		unsigned r1 = dtlb ?
		read_dtlb_translation(tlbidx) : read_itlb_translation(tlbidx);
		unsigned vpn = (r0 & PAGE_MASK) \| (e << PAGE_SHIFT);
		unsigned pte = get_pte_for_vaddr(vpn);
		unsigned mm_asid = (get_rasid_register() >> 8) & ASID_MASK;
		@@ -239,8 +241,6 @@ static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
		}

		if (tlb_asid == mm_asid) {
		unsigned r1 = dtlb ? read_dtlb_translation(tlbidx) :
		read_itlb_translation(tlbidx);
		if ((pte ^ r1) & PAGE_MASK) {
		pr_err("%cTLB: way: %u, entry: %u, mapping: %08x->%08x, PTE: %08x\n",
		dtlb ? 'D' : 'I', w, e, r0, r1, pte);

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