Commit 36d29fb5 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-3.11-dt' of... 

Merge tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

From Stephen Warren:
ARM: tegra: device tree updates

This branch contains all device tree updates for Tegra boards.

The changes are:

* Converted all DT files to use the C pre-processor, to support the use
  of named constants. This included use of defines for GPIO, IRQ, and
  clock constants.
* Enabling new features such as:
  - SPI on Dalmore.
  - Audio on Dalmore and Beaver.
  - gpio-leds on Beaver.
  - Power-supply/batter linkage on Dalmore.
* A minor fix to the RAM size node on Beaver.

It is based on previous pull request tegra-for-3.11-deps-for-usb
followed by a merge of tegra-for-3.11-deps-for-clk.

* tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra

: (21 commits)
  ARM: tegra: enable audio on Beaver
  ARM: tegra: enable audio on Dalmore
  ARM: tegra: add power-supplies link between battery and charger
  ARM: tegra: add audio-related nodes to Tegra114 DT
  ARM: tegra114: convert device tree files to use CLK defines
  ARM: tegra30: convert device tree files to use CLK defines
  ARM: tegra20: convert device tree files to use CLK defines
  ARM: tegra: Add charger subnode to tps65090 node
  ARM: tegra: convert device tree files to use IRQ defines
  ARM: tegra: convert device tree files to use GPIO defines
  ARM: tegra: create a DT header defining GPIO IDs
  ARM: tegra: use #include for all device trees
  ARM: tegra: Add gpio-leds to Tegra30 Beaver
  ARM: tegra: fix memory size on Beaver
  ARM: tegra: enable spi4 on Dalmore
  ARM: tegra114: create a DT header defining CLK IDs
  ARM: tegra30: create a DT header defining CLK IDs
  ARM: tegra20: create a DT header defining CLK IDs
  ARM: tegra: update device trees for USB binding rework
  ARM: tegra: modify ULPI reset GPIO properties
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3b2e6296 23037bbd

Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt

+4 −248
Original line number Diff line number Diff line
@@ -12,253 +12,9 @@ Required properties : 
- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the CAR.



  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB

  registers. These IDs often match those in the CAR's RST_DEVICES registers,

  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In

  this case, those clocks are assigned IDs above 160 in order to highlight

  this issue. Implementations that interpret these clock IDs as bit values

  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to

  explicitly handle these special cases.



  The balance of the clocks controlled by the CAR are assigned IDs of 160 and

  above.



  0	unassigned

  1	unassigned

  2	unassigned

  3	unassigned

  4	rtc

  5	timer

  6	uarta

  7	unassigned	(register bit affects uartb and vfir)

  8	unassigned

  9	sdmmc2

  10	unassigned	(register bit affects spdif_in and spdif_out)

  11	i2s1

  12	i2c1

  13	ndflash

  14	sdmmc1

  15	sdmmc4

  16	unassigned

  17	pwm

  18	i2s2

  19	epp

  20	unassigned	(register bit affects vi and vi_sensor)

  21	2d

  22	usbd

  23	isp

  24	3d

  25	unassigned

  26	disp2

  27	disp1

  28	host1x

  29	vcp

  30	i2s0

  31	unassigned



  32	unassigned

  33	unassigned

  34	apbdma

  35	unassigned

  36	kbc

  37	unassigned

  38	unassigned

  39	unassigned	(register bit affects fuse and fuse_burn)

  40	kfuse

  41	sbc1

  42	nor

  43	unassigned

  44	sbc2

  45	unassigned

  46	sbc3

  47	i2c5

  48	dsia

  49	unassigned

  50	mipi

  51	hdmi

  52	csi

  53	unassigned

  54	i2c2

  55	uartc

  56	mipi-cal

  57	emc

  58	usb2

  59	usb3

  60	msenc

  61	vde

  62	bsea

  63	bsev



  64	unassigned

  65	uartd

  66	unassigned

  67	i2c3

  68	sbc4

  69	sdmmc3

  70	unassigned

  71	owr

  72	afi

  73	csite

  74	unassigned

  75	unassigned

  76	la

  77	trace

  78	soc_therm

  79	dtv

  80	ndspeed

  81	i2cslow

  82	dsib

  83	tsec

  84	unassigned

  85	unassigned

  86	unassigned

  87	unassigned

  88	unassigned

  89	xusb_host

  90	unassigned

  91	msenc

  92	csus

  93	unassigned

  94	unassigned

  95	unassigned	(bit affects xusb_dev and xusb_dev_src)



  96	unassigned

  97	unassigned

  98	unassigned

  99	mselect

  100	tsensor

  101	i2s3

  102	i2s4

  103	i2c4

  104	sbc5

  105	sbc6

  106	d_audio

  107	apbif

  108	dam0

  109	dam1

  110	dam2

  111	hda2codec_2x

  112	unassigned

  113	audio0_2x

  114	audio1_2x

  115	audio2_2x

  116	audio3_2x

  117	audio4_2x

  118	spdif_2x

  119	actmon

  120	extern1

  121	extern2

  122	extern3

  123	unassigned

  124	unassigned

  125	hda

  126	unassigned

  127	se



  128	hda2hdmi

  129	unassigned

  130	unassigned

  131	unassigned

  132	unassigned

  133	unassigned

  134	unassigned

  135	unassigned

  136	unassigned

  137	unassigned

  138	unassigned

  139	unassigned

  140	unassigned

  141	unassigned

  142	unassigned

  143	unassigned	(bit affects xusb_falcon_src, xusb_fs_src,

			 xusb_host_src and xusb_ss_src)

  144	cilab

  145	cilcd

  146	cile

  147	dsialp

  148	dsiblp

  149	unassigned

  150	dds

  151	unassigned

  152	dp2

  153	amx

  154	adx

  155	unassigned	(bit affects dfll_ref and dfll_soc)

  156	xusb_ss



  192	uartb

  193	vfir

  194	spdif_in

  195	spdif_out

  196	vi

  197	vi_sensor

  198	fuse

  199	fuse_burn

  200	clk_32k

  201	clk_m

  202	clk_m_div2

  203	clk_m_div4

  204	pll_ref

  205	pll_c

  206	pll_c_out1

  207	pll_c2

  208	pll_c3

  209	pll_m

  210	pll_m_out1

  211	pll_p

  212	pll_p_out1

  213	pll_p_out2

  214	pll_p_out3

  215	pll_p_out4

  216	pll_a

  217	pll_a_out0

  218	pll_d

  219	pll_d_out0

  220	pll_d2

  221	pll_d2_out0

  222	pll_u

  223	pll_u_480M

  224	pll_u_60M

  225	pll_u_48M

  226	pll_u_12M

  227	pll_x

  228	pll_x_out0

  229	pll_re_vco

  230	pll_re_out

  231	pll_e_out0

  232	spdif_in_sync

  233	i2s0_sync

  234	i2s1_sync

  235	i2s2_sync

  236	i2s3_sync

  237	i2s4_sync

  238	vimclk_sync

  239	audio0

  240	audio1

  241	audio2

  242	audio3

  243	audio4

  244	spdif

  245	clk_out_1

  246	clk_out_2

  247	clk_out_3

  248	blink

  252	xusb_host_src

  253	xusb_falcon_src

  254	xusb_fs_src

  255	xusb_ss_src

  256	xusb_dev_src

  257	xusb_dev

  258	xusb_hs_src

  259	sclk

  260	hclk

  261	pclk

  262	cclk_g

  263	cclk_lp

  264	dfll_ref

  265	dfll_soc

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra114-car.h>.



Example SoC include file:
@@ -270,7 +26,7 @@ Example SoC include file: 
	};



	usb@c5004000 {

		clocks = <&tegra_car 58>; /* usb2 */

		clocks = <&tegra_car TEGRA114_CLK_USB2>;

	};

};

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

+4 −150
Original line number Diff line number Diff line
@@ -12,155 +12,9 @@ Required properties : 
- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the CAR.



  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB

  registers. These IDs often match those in the CAR's RST_DEVICES registers,

  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In

  this case, those clocks are assigned IDs above 95 in order to highlight

  this issue. Implementations that interpret these clock IDs as bit values

  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to

  explicitly handle these special cases.



  The balance of the clocks controlled by the CAR are assigned IDs of 96 and

  above.



  0	cpu

  1	unassigned

  2	unassigned

  3	ac97

  4	rtc

  5	tmr

  6	uart1

  7	unassigned	(register bit affects uart2 and vfir)

  8	gpio

  9	sdmmc2

  10	unassigned	(register bit affects spdif_in and spdif_out)

  11	i2s1

  12	i2c1

  13	ndflash

  14	sdmmc1

  15	sdmmc4

  16	twc

  17	pwm

  18	i2s2

  19	epp

  20	unassigned	(register bit affects vi and vi_sensor)

  21	2d

  22	usbd

  23	isp

  24	3d

  25	ide

  26	disp2

  27	disp1

  28	host1x

  29	vcp

  30	unassigned

  31	cache2



  32	mem

  33	ahbdma

  34	apbdma

  35	unassigned

  36	kbc

  37	stat_mon

  38	pmc

  39	fuse

  40	kfuse

  41	sbc1

  42	snor

  43	spi1

  44	sbc2

  45	xio

  46	sbc3

  47	dvc

  48	dsi

  49	unassigned	(register bit affects tvo and cve)

  50	mipi

  51	hdmi

  52	csi

  53	tvdac

  54	i2c2

  55	uart3

  56	unassigned

  57	emc

  58	usb2

  59	usb3

  60	mpe

  61	vde

  62	bsea

  63	bsev



  64	speedo

  65	uart4

  66	uart5

  67	i2c3

  68	sbc4

  69	sdmmc3

  70	pcie

  71	owr

  72	afi

  73	csite

  74	unassigned

  75	avpucq

  76	la

  77	unassigned

  78	unassigned

  79	unassigned

  80	unassigned

  81	unassigned

  82	unassigned

  83	unassigned

  84	irama

  85	iramb

  86	iramc

  87	iramd

  88	cram2

  89	audio_2x	a/k/a audio_2x_sync_clk

  90	clk_d

  91	unassigned

  92	sus

  93	cdev2

  94	cdev1

  95	unassigned



  96	uart2

  97	vfir

  98	spdif_in

  99	spdif_out

  100	vi

  101	vi_sensor

  102	tvo

  103	cve

  104	osc

  105	clk_32k		a/k/a clk_s

  106	clk_m

  107	sclk

  108	cclk

  109	hclk

  110	pclk

  111	blink

  112	pll_a

  113	pll_a_out0

  114	pll_c

  115	pll_c_out1

  116	pll_d

  117	pll_d_out0

  118	pll_e

  119	pll_m

  120	pll_m_out1

  121	pll_p

  122	pll_p_out1

  123	pll_p_out2

  124	pll_p_out3

  125	pll_p_out4

  126	pll_s

  127	pll_u

  128	pll_x

  129	cop		a/k/a avp

  130	audio		a/k/a audio_sync_clk

  131	pll_ref

  132	twd

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra20-car.h>.



Example SoC include file:
@@ -172,7 +26,7 @@ Example SoC include file: 
	};



	usb@c5004000 {

		clocks = <&tegra_car 58>; /* usb2 */

		clocks = <&tegra_car TEGRA20_CLK_USB2>;

	};

};

Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

+4 −207
Original line number Diff line number Diff line
@@ -12,212 +12,9 @@ Required properties : 
- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the CAR.



  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB

  registers. These IDs often match those in the CAR's RST_DEVICES registers,

  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In

  this case, those clocks are assigned IDs above 160 in order to highlight

  this issue. Implementations that interpret these clock IDs as bit values

  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to

  explicitly handle these special cases.



  The balance of the clocks controlled by the CAR are assigned IDs of 160 and

  above.



  0	cpu

  1	unassigned

  2	unassigned

  3	unassigned

  4	rtc

  5	timer

  6	uarta

  7	unassigned	(register bit affects uartb and vfir)

  8	gpio

  9	sdmmc2

  10	unassigned	(register bit affects spdif_in and spdif_out)

  11	i2s1

  12	i2c1

  13	ndflash

  14	sdmmc1

  15	sdmmc4

  16	unassigned

  17	pwm

  18	i2s2

  19	epp

  20	unassigned	(register bit affects vi and vi_sensor)

  21	2d

  22	usbd

  23	isp

  24	3d

  25	unassigned

  26	disp2

  27	disp1

  28	host1x

  29	vcp

  30	i2s0

  31	cop_cache



  32	mc

  33	ahbdma

  34	apbdma

  35	unassigned

  36	kbc

  37	statmon

  38	pmc

  39	unassigned	(register bit affects fuse and fuse_burn)

  40	kfuse

  41	sbc1

  42	nor

  43	unassigned

  44	sbc2

  45	unassigned

  46	sbc3

  47	i2c5

  48	dsia

  49	unassigned	(register bit affects cve and tvo)

  50	mipi

  51	hdmi

  52	csi

  53	tvdac

  54	i2c2

  55	uartc

  56	unassigned

  57	emc

  58	usb2

  59	usb3

  60	mpe

  61	vde

  62	bsea

  63	bsev



  64	speedo

  65	uartd

  66	uarte

  67	i2c3

  68	sbc4

  69	sdmmc3

  70	pcie

  71	owr

  72	afi

  73	csite

  74	pciex

  75	avpucq

  76	la

  77	unassigned

  78	unassigned

  79	dtv

  80	ndspeed

  81	i2cslow

  82	dsib

  83	unassigned

  84	irama

  85	iramb

  86	iramc

  87	iramd

  88	cram2

  89	unassigned

  90	audio_2x	a/k/a audio_2x_sync_clk

  91	unassigned

  92	csus

  93	cdev2

  94	cdev1

  95	unassigned



  96	cpu_g

  97	cpu_lp

  98	3d2

  99	mselect

  100	tsensor

  101	i2s3

  102	i2s4

  103	i2c4

  104	sbc5

  105	sbc6

  106	d_audio

  107	apbif

  108	dam0

  109	dam1

  110	dam2

  111	hda2codec_2x

  112	atomics

  113	audio0_2x

  114	audio1_2x

  115	audio2_2x

  116	audio3_2x

  117	audio4_2x

  118	audio5_2x

  119	actmon

  120	extern1

  121	extern2

  122	extern3

  123	sata_oob

  124	sata

  125	hda

  127	se

  128	hda2hdmi

  129	sata_cold



  160	uartb

  161	vfir

  162	spdif_in

  163	spdif_out

  164	vi

  165	vi_sensor

  166	fuse

  167	fuse_burn

  168	cve

  169	tvo



  170	clk_32k

  171	clk_m

  172	clk_m_div2

  173	clk_m_div4

  174	pll_ref

  175	pll_c

  176	pll_c_out1

  177	pll_m

  178	pll_m_out1

  179	pll_p

  180	pll_p_out1

  181	pll_p_out2

  182	pll_p_out3

  183	pll_p_out4

  184	pll_a

  185	pll_a_out0

  186	pll_d

  187	pll_d_out0

  188	pll_d2

  189	pll_d2_out0

  190	pll_u

  191	pll_x

  192	pll_x_out0

  193	pll_e

  194	spdif_in_sync

  195	i2s0_sync

  196	i2s1_sync

  197	i2s2_sync

  198	i2s3_sync

  199	i2s4_sync

  200	vimclk

  201	audio0

  202	audio1

  203	audio2

  204	audio3

  205	audio4

  206	audio5

  207	clk_out_1 (extern1)

  208	clk_out_2 (extern2)

  209	clk_out_3 (extern3)

  210	sclk

  211	blink

  212	cclk_g

  213	cclk_lp

  214	twd

  215	cml0

  216	cml1

  217	hclk

  218	pclk

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra30-car.h>.



Example SoC include file:
@@ -229,7 +26,7 @@ Example SoC include file: 
	};



	usb@c5004000 {

		clocks = <&tegra_car 58>; /* usb2 */

		clocks = <&tegra_car TEGRA30_CLK_USB2>;

	};

};

Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt

+5 −22
Original line number Diff line number Diff line
@@ -6,27 +6,10 @@ Practice : Universal Serial Bus" with the following modifications 
and additions :



Required properties :

 - compatible : Should be "nvidia,tegra20-ehci" for USB controllers

   used in host mode.

 - phy_type : Should be one of "ulpi" or "utmi".

 - nvidia,vbus-gpio : If present, specifies a gpio that needs to be

   activated for the bus to be powered.

 - nvidia,phy : phandle of the PHY instance, the controller is connected to.



Required properties for phy_type == ulpi:

  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.

 - compatible : Should be "nvidia,tegra20-ehci".

 - nvidia,phy : phandle of the PHY that the controller is connected to.

 - clocks : Contains a single entry which defines the USB controller's clock.



Optional properties:

  - dr_mode : dual role mode. Indicates the working mode for

   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",

   or "otg".  Default to "host" if not defined for backward compatibility.

      host means this is a host controller

      peripheral means it is device controller

      otg means it can operate as either ("on the go")

  - nvidia,has-legacy-mode : boolean indicates whether this controller can

    operate in legacy mode (as APX 2500 / 2600). In legacy mode some

    registers are accessed through the APB_MISC base address instead of

    the USB controller. Since this is a legacy issue it probably does not

    warrant a compatible string of its own.

  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2

 - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20

   USB ports, which need reset twice due to hardware issues.

Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt

+38 −3
Original line number Diff line number Diff line
@@ -4,14 +4,49 @@ The device node for Tegra SOC USB PHY: 


Required properties :

 - compatible : Should be "nvidia,tegra20-usb-phy".

 - reg : Address and length of the register set for the USB PHY interface.

 - phy_type : Should be one of "ulpi" or "utmi".

 - reg : Defines the following set of registers, in the order listed:

   - The PHY's own register set.

     Always present.

   - The register set of the PHY containing the UTMI pad control registers.

     Present if-and-only-if phy_type == utmi.

 - phy_type : Should be one of "utmi", "ulpi" or "hsic".

 - clocks : Defines the clocks listed in the clock-names property.

 - clock-names : The following clock names must be present:

   - reg: The clock needed to access the PHY's own registers. This is the

     associated EHCI controller's clock. Always present.

   - pll_u: PLL_U. Always present.

   - timer: The timeout clock (clk_m). Present if phy_type == utmi.

   - utmi-pads: The clock needed to access the UTMI pad control registers.

     Present if phy_type == utmi.

   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).

     Present if phy_type == ulpi, and ULPI link mode is in use.



Required properties for phy_type == ulpi:

  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.



Required PHY timing params for utmi phy:

  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before

    start of sync launches RxActive

  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store

  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait

    before declare IDLE.

  - nvidia,term-range-adj : Range adjusment on terminations

  - nvidia,xcvr-setup : HS driver output control

  - nvidia,xcvr-lsfslew : LS falling slew rate control.

  - nvidia,xcvr-lsrslew :  LS rising slew rate control.



Optional properties:

  - nvidia,has-legacy-mode : boolean indicates whether this controller can

    operate in legacy mode (as APX 2500 / 2600). In legacy mode some

    registers are accessed through the APB_MISC base address instead of

    the USB controller.

  - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power

    optimizations for the devices that are always connected. e.g. modem.

  - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be

    "host", "peripheral", or "otg". Defaults to "host" if not defined.

      host means this is a host controller

      peripheral means it is device controller

      otg means it can operate as either ("on the go")



Required properties for dr_mode == otg:

  - vbus-supply: regulator for VBUS

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