Commit 36d26912 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Add support for DCN302 (v2) 



 - add DCN302 resource, irq service, dmub loader,
 - handle  DC_VERSION_DCN_3_02
 - define DCN302 power gating functions
 - handle DCN302 in GPIO files
 - define I2C regs
 - add CONFIG_DRM_AMD_DC_DCN3_02 guard

v2: rebase fixes (Alex)

Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4da67839

drivers/gpu/drm/amd/display/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -34,6 +34,13 @@ config DRM_AMD_DC_DCN3_01 
	    Choose this option if you want to have

	    Van Gogh support for display engine



config DRM_AMD_DC_DCN3_02

        bool "DCN 3.02 family"

        depends on DRM_AMD_DC_DCN3_0

        help

            Choose this option if you want to have

            Dimgrey_cavefish support for display engine



config DRM_AMD_DC_HDCP

	bool "Enable HDCP support in DC"

	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/dc/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -40,6 +40,11 @@ ifdef CONFIG_DRM_AMD_DC_DCN3_01 
DC_LIBS += dcn301

endif



ifdef CONFIG_DRM_AMD_DC_DCN3_02

DC_LIBS += dcn302



endif



DC_LIBS += dce120



DC_LIBS += dce112

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

+5 −0
Original line number Diff line number Diff line
@@ -82,6 +82,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
	case DCN_VERSION_3_01:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case DCN_VERSION_3_02:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif

	default:

		/* Unsupported DCE */

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+6 −0
Original line number Diff line number Diff line
@@ -186,6 +186,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			break;

		}

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {

			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			break;

		}

#endif

#endif

		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

		break;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+13 −0
Original line number Diff line number Diff line
@@ -61,6 +61,9 @@ 
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

#include "../dcn301/dcn301_resource.h"

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

#include "../dcn302/dcn302_resource.h"

#endif



#define DC_LOGGER_INIT(logger)
@@ -131,6 +134,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))

			dc_version = DCN_VERSION_3_0;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))

			dc_version = DCN_VERSION_3_02;

#endif

		break;
@@ -223,6 +230,12 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, 
	case DCN_VERSION_3_01:

		res_pool = dcn301_create_resource_pool(init_data, dc);

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case DCN_VERSION_3_02:

		res_pool = dcn302_create_resource_pool(init_data, dc);

		break;



#endif

	default:

		break;

CRA Git | Maintained and supported by SUSTech CRA and CCSE