net: mvpp2: restructure "link status" interrupt handling (36cfd3a6) · Commits · 戴 / test

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+51 −32

Original line number	Diff line number	Diff line
		@@ -2974,62 +2974,81 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id)
		return IRQ_HANDLED;
		}

		/* Per-port interrupt for link status changes */
		static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
		static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
		{
		struct mvpp2_port port = (struct mvpp2_port )dev_id;
		struct net_device *dev = port->dev;
		bool event = false, link = false;
		u32 val;

		mvpp22_gop_mask_irq(port);
		if (port->phylink) {
		phylink_mac_change(port->phylink, link);
		return;
		}

		if (!netif_running(dev))
		return;

		if (link) {
		mvpp2_interrupts_enable(port);

		mvpp2_egress_enable(port);
		mvpp2_ingress_enable(port);
		netif_carrier_on(dev);
		netif_tx_wake_all_queues(dev);
		} else {
		netif_tx_stop_all_queues(dev);
		netif_carrier_off(dev);
		mvpp2_ingress_disable(port);
		mvpp2_egress_disable(port);

		mvpp2_interrupts_disable(port);
		}
		}

		static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
		{
		bool link;
		u32 val;

		if (mvpp2_port_supports_xlg(port) &&
		mvpp2_is_xlg(port->phy_interface)) {
		val = readl(port->base + MVPP22_XLG_INT_STAT);
		if (val & MVPP22_XLG_INT_STAT_LINK) {
		event = true;
		val = readl(port->base + MVPP22_XLG_STATUS);
		if (val & MVPP22_XLG_STATUS_LINK_UP)
		link = true;
		mvpp2_isr_handle_link(port, link);
		}
		}
		} else if (phy_interface_mode_is_rgmii(port->phy_interface) \|\|

		static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
		{
		bool link;
		u32 val;

		if (phy_interface_mode_is_rgmii(port->phy_interface) \|\|
		phy_interface_mode_is_8023z(port->phy_interface) \|\|
		port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
		val = readl(port->base + MVPP22_GMAC_INT_STAT);
		if (val & MVPP22_GMAC_INT_STAT_LINK) {
		event = true;
		val = readl(port->base + MVPP2_GMAC_STATUS0);
		if (val & MVPP2_GMAC_STATUS0_LINK_UP)
		link = true;
		mvpp2_isr_handle_link(port, link);
		}
		}

		if (port->phylink) {
		phylink_mac_change(port->phylink, link);
		goto handled;
		}

		if (!netif_running(dev) \|\| !event)
		goto handled;
		/* Per-port interrupt for link status changes */
		static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
		{
		struct mvpp2_port port = (struct mvpp2_port )dev_id;

		if (link) {
		mvpp2_interrupts_enable(port);
		mvpp22_gop_mask_irq(port);

		mvpp2_egress_enable(port);
		mvpp2_ingress_enable(port);
		netif_carrier_on(dev);
		netif_tx_wake_all_queues(dev);
		if (mvpp2_port_supports_xlg(port) &&
		mvpp2_is_xlg(port->phy_interface)) {
		mvpp2_isr_handle_xlg(port);
		} else {
		netif_tx_stop_all_queues(dev);
		netif_carrier_off(dev);
		mvpp2_ingress_disable(port);
		mvpp2_egress_disable(port);

		mvpp2_interrupts_disable(port);
		mvpp2_isr_handle_gmac_internal(port);
		}

		handled:
		mvpp22_gop_unmask_irq(port);
		return IRQ_HANDLED;
		}

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