Merge tag 'kvm-arm-for-v4.12-round2' of... (36c344f3) · Commits · 戴 / test

Documentation/virtual/kvm/devices/arm-vgic-its.txt

+121 −0

Original line number	Diff line number	Diff line
		@@ -32,7 +32,128 @@ Groups:
		KVM_DEV_ARM_VGIC_CTRL_INIT
		request the initialization of the ITS, no additional parameter in
		kvm_device_attr.addr.

		KVM_DEV_ARM_ITS_SAVE_TABLES
		save the ITS table data into guest RAM, at the location provisioned
		by the guest in corresponding registers/table entries.

		The layout of the tables in guest memory defines an ABI. The entries
		are laid out in little endian format as described in the last paragraph.

		KVM_DEV_ARM_ITS_RESTORE_TABLES
		restore the ITS tables from guest RAM to ITS internal structures.

		The GICV3 must be restored before the ITS and all ITS registers but
		the GITS_CTLR must be restored before restoring the ITS tables.

		The GITS_IIDR read-only register must also be restored before
		calling KVM_DEV_ARM_ITS_RESTORE_TABLES as the IIDR revision field
		encodes the ABI revision.

		The expected ordering when restoring the GICv3/ITS is described in section
		"ITS Restore Sequence".

		Errors:
		-ENXIO: ITS not properly configured as required prior to setting
		this attribute
		-ENOMEM: Memory shortage when allocating ITS internal data
		-EINVAL: Inconsistent restored data
		-EFAULT: Invalid guest ram access
		-EBUSY: One or more VCPUS are running

		KVM_DEV_ARM_VGIC_GRP_ITS_REGS
		Attributes:
		The attr field of kvm_device_attr encodes the offset of the
		ITS register, relative to the ITS control frame base address
		(ITS_base).

		kvm_device_attr.addr points to a __u64 value whatever the width
		of the addressed register (32/64 bits). 64 bit registers can only
		be accessed with full length.

		Writes to read-only registers are ignored by the kernel except for:
		- GITS_CREADR. It must be restored otherwise commands in the queue
		will be re-executed after restoring CWRITER. GITS_CREADR must be
		restored before restoring the GITS_CTLR which is likely to enable the
		ITS. Also it must be restored after GITS_CBASER since a write to
		GITS_CBASER resets GITS_CREADR.
		- GITS_IIDR. The Revision field encodes the table layout ABI revision.
		In the future we might implement direct injection of virtual LPIs.
		This will require an upgrade of the table layout and an evolution of
		the ABI. GITS_IIDR must be restored before calling
		KVM_DEV_ARM_ITS_RESTORE_TABLES.

		For other registers, getting or setting a register has the same
		effect as reading/writing the register on real hardware.
		Errors:
		-ENXIO: Offset does not correspond to any supported register
		-EFAULT: Invalid user pointer for attr->addr
		-EINVAL: Offset is not 64-bit aligned
		-EBUSY: one or more VCPUS are running

		ITS Restore Sequence:
		-------------------------

		The following ordering must be followed when restoring the GIC and the ITS:
		a) restore all guest memory and create vcpus
		b) restore all redistributors
		c) provide the its base address
		(KVM_DEV_ARM_VGIC_GRP_ADDR)
		d) restore the ITS in the following order:
		1. Restore GITS_CBASER
		2. Restore all other GITS_ registers, except GITS_CTLR!
		3. Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES)
		4. Restore GITS_CTLR

		Then vcpus can be started.

		ITS Table ABI REV0:
		-------------------

		Revision 0 of the ABI only supports the features of a virtual GICv3, and does
		not support a virtual GICv4 with support for direct injection of virtual
		interrupts for nested hypervisors.

		The device table and ITT are indexed by the DeviceID and EventID,
		respectively. The collection table is not indexed by CollectionID, and the
		entries in the collection are listed in no particular order.
		All entries are 8 bytes.

		Device Table Entry (DTE):

		bits: \| 63\| 62 ... 49 \| 48 ... 5 \| 4 ... 0 \|
		values: \| V \| next \| ITT_addr \| Size \|

		where;
		- V indicates whether the entry is valid. If not, other fields
		are not meaningful.
		- next: equals to 0 if this entry is the last one; otherwise it
		corresponds to the DeviceID offset to the next DTE, capped by
		2^14 -1.
		- ITT_addr matches bits [51:8] of the ITT address (256 Byte aligned).
		- Size specifies the supported number of bits for the EventID,
		minus one

		Collection Table Entry (CTE):

		bits: \| 63\| 62 .. 52 \| 51 ... 16 \| 15 ... 0 \|
		values: \| V \| RES0 \| RDBase \| ICID \|

		where:
		- V indicates whether the entry is valid. If not, other fields are
		not meaningful.
		- RES0: reserved field with Should-Be-Zero-or-Preserved behavior.
		- RDBase is the PE number (GICR_TYPER.Processor_Number semantic),
		- ICID is the collection ID

		Interrupt Translation Entry (ITE):

		bits: \| 63 ... 48 \| 47 ... 16 \| 15 ... 0 \|
		values: \| next \| pINTID \| ICID \|

		where:
		- next: equals to 0 if this entry is the last one; otherwise it corresponds
		to the EventID offset to the next ITE capped by 2^16 -1.
		- pINTID is the physical LPI ID; if zero, it means the entry is not valid
		and other fields are not meaningful.
		- ICID is the collection ID

Documentation/virtual/kvm/devices/arm-vgic-v3.txt

+6 −0

Original line number	Diff line number	Diff line
		@@ -167,11 +167,17 @@ Groups:
		KVM_DEV_ARM_VGIC_CTRL_INIT
		request the initialization of the VGIC, no additional parameter in
		kvm_device_attr.addr.
		KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
		save all LPI pending bits into guest RAM pending tables.

		The first kB of the pending table is not altered by this operation.
		Errors:
		-ENXIO: VGIC not properly configured as required prior to calling
		this attribute
		-ENODEV: no online VCPU
		-ENOMEM: memory shortage when allocating vgic internal data
		-EFAULT: Invalid guest ram access
		-EBUSY: One or more VCPUS are running


		KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO

arch/arm/include/uapi/asm/kvm.h

+5 −1

Original line number	Diff line number	Diff line
		@@ -196,6 +196,7 @@ struct kvm_arch_memory_slot {
		#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
		#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
		#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
		#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
		#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
		#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
		(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
		@@ -203,6 +204,9 @@ struct kvm_arch_memory_slot {
		#define VGIC_LEVEL_INFO_LINE_LEVEL 0

		#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
		#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
		#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
		#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3

		/* KVM_IRQ_LINE irq field index values */
		#define KVM_ARM_IRQ_TYPE_SHIFT 24

arch/arm/kvm/Makefile

+5 −2

Original line number	Diff line number	Diff line
		@@ -18,9 +18,12 @@ KVM := ../../../virt/kvm
		kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o

		obj-$(CONFIG_KVM_ARM_HOST) += hyp/

		obj-y += kvm-arm.o init.o interrupts.o
		obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
		obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o vgic-v3-coproc.o
		obj-y += handle_exit.o guest.o emulate.o reset.o
		obj-y += coproc.o coproc_a15.o coproc_a7.o vgic-v3-coproc.o
		obj-y += $(KVM)/arm/arm.o $(KVM)/arm/mmu.o $(KVM)/arm/mmio.o
		obj-y += $(KVM)/arm/psci.o $(KVM)/arm/perf.o
		obj-y += $(KVM)/arm/aarch32.o

		obj-y += $(KVM)/arm/vgic/vgic.o

arch/arm/kvm/trace.h

+0 −247

Original line number	Diff line number	Diff line
		@@ -6,133 +6,6 @@
		#undef TRACE_SYSTEM
		#define TRACE_SYSTEM kvm

		/*
		* Tracepoints for entry/exit to guest
		*/
		TRACE_EVENT(kvm_entry,
		TP_PROTO(unsigned long vcpu_pc),
		TP_ARGS(vcpu_pc),

		TP_STRUCT__entry(
		__field( unsigned long, vcpu_pc )
		),

		TP_fast_assign(
		__entry->vcpu_pc = vcpu_pc;
		),

		TP_printk("PC: 0x%08lx", __entry->vcpu_pc)
		);

		TRACE_EVENT(kvm_exit,
		TP_PROTO(int idx, unsigned int exit_reason, unsigned long vcpu_pc),
		TP_ARGS(idx, exit_reason, vcpu_pc),

		TP_STRUCT__entry(
		__field( int, idx )
		__field( unsigned int, exit_reason )
		__field( unsigned long, vcpu_pc )
		),

		TP_fast_assign(
		__entry->idx = idx;
		__entry->exit_reason = exit_reason;
		__entry->vcpu_pc = vcpu_pc;
		),

		TP_printk("%s: HSR_EC: 0x%04x (%s), PC: 0x%08lx",
		__print_symbolic(__entry->idx, kvm_arm_exception_type),
		__entry->exit_reason,
		__print_symbolic(__entry->exit_reason, kvm_arm_exception_class),
		__entry->vcpu_pc)
		);

		TRACE_EVENT(kvm_guest_fault,
		TP_PROTO(unsigned long vcpu_pc, unsigned long hsr,
		unsigned long hxfar,
		unsigned long long ipa),
		TP_ARGS(vcpu_pc, hsr, hxfar, ipa),

		TP_STRUCT__entry(
		__field( unsigned long, vcpu_pc )
		__field( unsigned long, hsr )
		__field( unsigned long, hxfar )
		__field( unsigned long long, ipa )
		),

		TP_fast_assign(
		__entry->vcpu_pc = vcpu_pc;
		__entry->hsr = hsr;
		__entry->hxfar = hxfar;
		__entry->ipa = ipa;
		),

		TP_printk("ipa %#llx, hsr %#08lx, hxfar %#08lx, pc %#08lx",
		__entry->ipa, __entry->hsr,
		__entry->hxfar, __entry->vcpu_pc)
		);

		TRACE_EVENT(kvm_access_fault,
		TP_PROTO(unsigned long ipa),
		TP_ARGS(ipa),

		TP_STRUCT__entry(
		__field( unsigned long, ipa )
		),

		TP_fast_assign(
		__entry->ipa = ipa;
		),

		TP_printk("IPA: %lx", __entry->ipa)
		);

		TRACE_EVENT(kvm_irq_line,
		TP_PROTO(unsigned int type, int vcpu_idx, int irq_num, int level),
		TP_ARGS(type, vcpu_idx, irq_num, level),

		TP_STRUCT__entry(
		__field( unsigned int, type )
		__field( int, vcpu_idx )
		__field( int, irq_num )
		__field( int, level )
		),

		TP_fast_assign(
		__entry->type = type;
		__entry->vcpu_idx = vcpu_idx;
		__entry->irq_num = irq_num;
		__entry->level = level;
		),

		TP_printk("Inject %s interrupt (%d), vcpu->idx: %d, num: %d, level: %d",
		(__entry->type == KVM_ARM_IRQ_TYPE_CPU) ? "CPU" :
		(__entry->type == KVM_ARM_IRQ_TYPE_PPI) ? "VGIC PPI" :
		(__entry->type == KVM_ARM_IRQ_TYPE_SPI) ? "VGIC SPI" : "UNKNOWN",
		__entry->type, __entry->vcpu_idx, __entry->irq_num, __entry->level)
		);

		TRACE_EVENT(kvm_mmio_emulate,
		TP_PROTO(unsigned long vcpu_pc, unsigned long instr,
		unsigned long cpsr),
		TP_ARGS(vcpu_pc, instr, cpsr),

		TP_STRUCT__entry(
		__field( unsigned long, vcpu_pc )
		__field( unsigned long, instr )
		__field( unsigned long, cpsr )
		),

		TP_fast_assign(
		__entry->vcpu_pc = vcpu_pc;
		__entry->instr = instr;
		__entry->cpsr = cpsr;
		),

		TP_printk("Emulate MMIO at: 0x%08lx (instr: %08lx, cpsr: %08lx)",
		__entry->vcpu_pc, __entry->instr, __entry->cpsr)
		);

		/* Architecturally implementation defined CP15 register access */
		TRACE_EVENT(kvm_emulate_cp15_imp,
		TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
		@@ -181,87 +54,6 @@ TRACE_EVENT(kvm_wfx,
		__entry->is_wfe ? 'e' : 'i', __entry->vcpu_pc)
		);

		TRACE_EVENT(kvm_unmap_hva,
		TP_PROTO(unsigned long hva),
		TP_ARGS(hva),

		TP_STRUCT__entry(
		__field( unsigned long, hva )
		),

		TP_fast_assign(
		__entry->hva = hva;
		),

		TP_printk("mmu notifier unmap hva: %#08lx", __entry->hva)
		);

		TRACE_EVENT(kvm_unmap_hva_range,
		TP_PROTO(unsigned long start, unsigned long end),
		TP_ARGS(start, end),

		TP_STRUCT__entry(
		__field( unsigned long, start )
		__field( unsigned long, end )
		),

		TP_fast_assign(
		__entry->start = start;
		__entry->end = end;
		),

		TP_printk("mmu notifier unmap range: %#08lx -- %#08lx",
		__entry->start, __entry->end)
		);

		TRACE_EVENT(kvm_set_spte_hva,
		TP_PROTO(unsigned long hva),
		TP_ARGS(hva),

		TP_STRUCT__entry(
		__field( unsigned long, hva )
		),

		TP_fast_assign(
		__entry->hva = hva;
		),

		TP_printk("mmu notifier set pte hva: %#08lx", __entry->hva)
		);

		TRACE_EVENT(kvm_age_hva,
		TP_PROTO(unsigned long start, unsigned long end),
		TP_ARGS(start, end),

		TP_STRUCT__entry(
		__field( unsigned long, start )
		__field( unsigned long, end )
		),

		TP_fast_assign(
		__entry->start = start;
		__entry->end = end;
		),

		TP_printk("mmu notifier age hva: %#08lx -- %#08lx",
		__entry->start, __entry->end)
		);

		TRACE_EVENT(kvm_test_age_hva,
		TP_PROTO(unsigned long hva),
		TP_ARGS(hva),

		TP_STRUCT__entry(
		__field( unsigned long, hva )
		),

		TP_fast_assign(
		__entry->hva = hva;
		),

		TP_printk("mmu notifier test age hva: %#08lx", __entry->hva)
		);

		TRACE_EVENT(kvm_hvc,
		TP_PROTO(unsigned long vcpu_pc, unsigned long r0, unsigned long imm),
		TP_ARGS(vcpu_pc, r0, imm),
		@@ -282,45 +74,6 @@ TRACE_EVENT(kvm_hvc,
		__entry->vcpu_pc, __entry->r0, __entry->imm)
		);

		TRACE_EVENT(kvm_set_way_flush,
		TP_PROTO(unsigned long vcpu_pc, bool cache),
		TP_ARGS(vcpu_pc, cache),

		TP_STRUCT__entry(
		__field( unsigned long, vcpu_pc )
		__field( bool, cache )
		),

		TP_fast_assign(
		__entry->vcpu_pc = vcpu_pc;
		__entry->cache = cache;
		),

		TP_printk("S/W flush at 0x%016lx (cache %s)",
		__entry->vcpu_pc, __entry->cache ? "on" : "off")
		);

		TRACE_EVENT(kvm_toggle_cache,
		TP_PROTO(unsigned long vcpu_pc, bool was, bool now),
		TP_ARGS(vcpu_pc, was, now),

		TP_STRUCT__entry(
		__field( unsigned long, vcpu_pc )
		__field( bool, was )
		__field( bool, now )
		),

		TP_fast_assign(
		__entry->vcpu_pc = vcpu_pc;
		__entry->was = was;
		__entry->now = now;
		),

		TP_printk("VM op at 0x%016lx (cache was %s, now %s)",
		__entry->vcpu_pc, __entry->was ? "on" : "off",
		__entry->now ? "on" : "off")
		);

		#endif /* _TRACE_KVM_H */

		#undef TRACE_INCLUDE_PATH

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