Commit 36b6b681 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Chris Wilson
Browse files

drm/i915: Fix MOCS PTE setting for gen9+ 



Fix up the MOCS PTE setting to really get the LLC cacheability
from the PTE rather than hardocoding it to LLC or LLC+eLLC.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007120329.17076-2-ville.syrjala@linux.intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20201015122138.30161-2-chris@chris-wilson.co.uk
parent d46b60a2

drivers/gpu/drm/i915/gt/intel_mocs.c

+2 −2
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ struct drm_i915_mocs_table { 
		   LE_1_UC | LE_TC_2_LLC_ELLC, \

		   L3_1_UC), \

	MOCS_ENTRY(I915_MOCS_PTE, \

		   LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \

		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \

		   L3_3_WB)



static const struct drm_i915_mocs_entry skl_mocs_table[] = {
@@ -280,7 +280,7 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = { 
		   L3_1_UC),

	/* Base - L3 + LeCC:PAT (Deprecated) */

	MOCS_ENTRY(I915_MOCS_PTE,

		   LE_0_PAGETABLE | LE_TC_1_LLC,

		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE,

		   L3_3_WB),



	GEN11_MOCS_ENTRIES

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