Commit 36ab3e73 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: dt: sun7i: Add A20 SPI controller nodes 



The A20 has 4 SPI controllers compatible with the one found in the A10. Add
them in the DT.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 5991bbe4

arch/arm/boot/dts/sun7i-a20.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -401,6 +401,28 @@ 
		#size-cells = <1>;

		ranges;



		spi0: spi@01c05000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c05000 0x1000>;

			interrupts = <0 10 4>;

			clocks = <&ahb_gates 20>, <&spi0_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@01c06000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c06000 0x1000>;

			interrupts = <0 11 4>;

			clocks = <&ahb_gates 21>, <&spi1_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		emac: ethernet@01c0b000 {

			compatible = "allwinner,sun4i-emac";

			reg = <0x01c0b000 0x1000>;
@@ -417,6 +439,28 @@ 
			#size-cells = <0>;

		};



		spi2: spi@01c17000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c17000 0x1000>;

			interrupts = <0 12 4>;

			clocks = <&ahb_gates 22>, <&spi2_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi3: spi@01c1f000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c1f000 0x1000>;

			interrupts = <0 50 4>;

			clocks = <&ahb_gates 23>, <&spi3_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun7i-a20-pinctrl";

			reg = <0x01c20800 0x400>;

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