Commit 369b7ebe authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add wm table for Renoir 



[Why]
Without additional HostVM Latency, Renoir takes 2us longer to exit
self-refresh. This causes underflow in certain cases.

[How]
Add table for Renoir with updated sr exit latencies for WM set A.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c2ffe78b

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+89 −4
Original line number Diff line number Diff line
@@ -579,7 +579,7 @@ static struct clk_bw_params rn_bw_params = { 


};



static struct wm_table ddr4_wm_table = {

static struct wm_table ddr4_wm_table_gs = {

	.entries = {

		{

			.wm_inst = WM_A,
@@ -616,7 +616,7 @@ static struct wm_table ddr4_wm_table = { 
	}

};



static struct wm_table lpddr4_wm_table = {

static struct wm_table lpddr4_wm_table_gs = {

	.entries = {

		{

			.wm_inst = WM_A,
@@ -690,6 +690,80 @@ static struct wm_table lpddr4_wm_table_with_disabled_ppt = { 
	}

};



static struct wm_table ddr4_wm_table_rn = {

	.entries = {

		{

			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9.09,

			.sr_enter_plus_exit_time_us = 10.14,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 10.12,

			.sr_enter_plus_exit_time_us = 11.48,

			.valid = true,

		},

	}

};



static struct wm_table lpddr4_wm_table_rn = {

	.entries = {

		{

			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 7.32,

			.sr_enter_plus_exit_time_us = 8.38,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.82,

			.sr_enter_plus_exit_time_us = 11.196,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.89,

			.sr_enter_plus_exit_time_us = 11.24,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.748,

			.sr_enter_plus_exit_time_us = 11.102,

			.valid = true,

		},

	}

};



static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)

{

	int i;
@@ -771,6 +845,11 @@ void rn_clk_mgr_construct( 
	struct dc_debug_options *debug = &ctx->dc->debug;

	struct dpm_clocks clock_table = { 0 };

	enum pp_smu_status status = 0;

	int is_green_sardine = 0;



#if defined(CONFIG_DRM_AMD_DC_DCN)

	is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);

#endif



	clk_mgr->base.ctx = ctx;

	clk_mgr->base.funcs = &dcn21_funcs;
@@ -811,10 +890,16 @@ void rn_clk_mgr_construct( 
			if (clk_mgr->periodic_retraining_disabled) {

				rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;

			} else {

				rn_bw_params.wm_table = lpddr4_wm_table;

				if (is_green_sardine)

					rn_bw_params.wm_table = lpddr4_wm_table_gs;

				else

					rn_bw_params.wm_table = lpddr4_wm_table_rn;

			}

		} else {

			rn_bw_params.wm_table = ddr4_wm_table;

			if (is_green_sardine)

				rn_bw_params.wm_table = ddr4_wm_table_gs;

			else

				rn_bw_params.wm_table = ddr4_wm_table_rn;

		}

		/* Saved clocks configured at boot for debug purposes */

		rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

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